On Thu, May 5, 2016 at 6:04 PM, Michael S. Tsirkin wrote:
> On Thu, May 05, 2016 at 05:27:03PM +0200, Ladi Prosek wrote:
>> On Thu, May 5, 2016 at 5:20 PM, Michael S. Tsirkin wrote:
>> > On Thu, May 05, 2016 at 05:15:01PM +0200, Ladi Prosek wrote:
>> >> On Thu, May 5, 2016 at 5:02 PM, Michael S.
On Thu, May 05, 2016 at 05:27:03PM +0200, Ladi Prosek wrote:
> On Thu, May 5, 2016 at 5:20 PM, Michael S. Tsirkin wrote:
> > On Thu, May 05, 2016 at 05:15:01PM +0200, Ladi Prosek wrote:
> >> On Thu, May 5, 2016 at 5:02 PM, Michael S. Tsirkin wrote:
> >> > On Thu, May 05, 2016 at 04:59:13PM +0200,
On Thu, May 5, 2016 at 5:20 PM, Michael S. Tsirkin wrote:
> On Thu, May 05, 2016 at 05:15:01PM +0200, Ladi Prosek wrote:
>> On Thu, May 5, 2016 at 5:02 PM, Michael S. Tsirkin wrote:
>> > On Thu, May 05, 2016 at 04:59:13PM +0200, Ladi Prosek wrote:
>> >> On Thu, May 5, 2016 at 3:36 PM, Michael S.
On Thu, May 05, 2016 at 05:15:01PM +0200, Ladi Prosek wrote:
> On Thu, May 5, 2016 at 5:02 PM, Michael S. Tsirkin wrote:
> > On Thu, May 05, 2016 at 04:59:13PM +0200, Ladi Prosek wrote:
> >> On Thu, May 5, 2016 at 3:36 PM, Michael S. Tsirkin wrote:
> >> > On Thu, May 05, 2016 at 11:13:37AM +0200,
On Thu, May 5, 2016 at 5:02 PM, Michael S. Tsirkin wrote:
> On Thu, May 05, 2016 at 04:59:13PM +0200, Ladi Prosek wrote:
>> On Thu, May 5, 2016 at 3:36 PM, Michael S. Tsirkin wrote:
>> > On Thu, May 05, 2016 at 11:13:37AM +0200, Ladi Prosek wrote:
>> >> There is a discrepancy between dataplane an
On Thu, May 05, 2016 at 04:59:13PM +0200, Ladi Prosek wrote:
> On Thu, May 5, 2016 at 3:36 PM, Michael S. Tsirkin wrote:
> > On Thu, May 05, 2016 at 11:13:37AM +0200, Ladi Prosek wrote:
> >> There is a discrepancy between dataplane and no-dataplane virtio
> >> behavior with respect to the ISR stat
On Thu, May 5, 2016 at 3:36 PM, Michael S. Tsirkin wrote:
> On Thu, May 05, 2016 at 11:13:37AM +0200, Ladi Prosek wrote:
>> There is a discrepancy between dataplane and no-dataplane virtio
>> behavior with respect to the ISR status register and MSI-X
>> capability.
>>
>> Without dataplane the Queu
On Thu, May 05, 2016 at 11:13:37AM +0200, Ladi Prosek wrote:
> There is a discrepancy between dataplane and no-dataplane virtio
> behavior with respect to the ISR status register and MSI-X
> capability.
>
> Without dataplane the Queue interrupt ISR status bit is set
> regardless of how the notific
There is a discrepancy between dataplane and no-dataplane virtio
behavior with respect to the ISR status register and MSI-X
capability.
Without dataplane the Queue interrupt ISR status bit is set
regardless of how the notification is delivered to the guest.
With dataplane the Queue interrupt ISR