On 14/06/2018 23:14, Richard Henderson wrote:
> On 06/14/2018 08:19 AM, Paolo Bonzini wrote:
>> But why isn't the parallel port at 0x378? That's the expected place on
>> PC (the second parallel port is at 0x278 and the third is at 0x3bc), and
>> I would expect other SuperIO chips to have it there
On 06/14/2018 08:19 AM, Paolo Bonzini wrote:
> But why isn't the parallel port at 0x378? That's the expected place on
> PC (the second parallel port is at 0x278 and the third is at 0x3bc), and
> I would expect other SuperIO chips to have it there too. That would be
> a one line fix.
Agreed.
On 14/06/2018 20:01, Philippe Mathieu-Daudé wrote:
> +
> +static Property smc37c669_properties[] = {
> +DEFINE_PROP_UINT32("config", SMC37C669State, config, 0x78889c28),
> +DEFINE_PROP_BIT("parallel", SMC37C669State, config, 8 + 2, true),
> +DEFINE_PROP_END_OF_LIST()
> +};
I would
The Config Register 0..3 are used by the BIOS to enable functionalities.
The FDC37C669 incorporates Software Configurable Logic (SCL)
for ease of use. Use of the SCL feature allows programmable
system configuration of key functions such as the FDC,
parallel port, and UARTs.
