On 26 October 2015 at 07:43, Pavel Fedin wrote:
> Hello!
>
> I skipped many of comments because they are straightforward to address,
> decided to discuss only important ones.
>
>> So we're going to (potentially) emulate:
>> * non-system-register config
>> * non-affinity-routing config
>>
>> ?
Hello!
I skipped many of comments because they are straightforward to address,
decided to discuss only important ones.
> So we're going to (potentially) emulate:
> * non-system-register config
> * non-affinity-routing config
>
> ? OK, but are we really sure we want to do that? Legacy config
On 24 October 2015 at 13:30, Shlomo Pongratz wrote:
> Comment on the "workaround" see inline.
>
>> > +/* Workaround!
>> > + * Linux (drivers/irqchip/irq-gic-v3.c) is enabling only group
>> > one,
>> > + * in gic_cpu_sys_reg_init it calls gic_write_grpen1(1);
>> > +
Comment on the "workaround" see inline.
On Friday, October 23, 2015, Peter Maydell wrote:
> On 22 October 2015 at 15:02, Pavel Fedin > wrote:
> > Add state information to GICv3 object structure and implement
> > arm_gicv3_common_reset(). Also, add some functions for registers which
> are
> > no
On 22 October 2015 at 15:02, Pavel Fedin wrote:
> Add state information to GICv3 object structure and implement
> arm_gicv3_common_reset(). Also, add some functions for registers which are
> not stored directly but simulated.
>
> State information includes not only pure GICv3 data, but also some l
Add state information to GICv3 object structure and implement
arm_gicv3_common_reset(). Also, add some functions for registers which are
not stored directly but simulated.
State information includes not only pure GICv3 data, but also some legacy
registers. This will be useful for implementing soft
