On 13/06/2019 12:01, Fabiano Rosas wrote:
> Alexey Kardashevskiy writes:
>
>> It is TCG, a single CPU with a single thread and no matter where I put
>
> Ok, but then none of this code gets executed because it is kvm-only:
I was not clear, this is a generic issue, not related to your patchse
Alexey Kardashevskiy writes:
> It is TCG, a single CPU with a single thread and no matter where I put
Ok, but then none of this code gets executed because it is kvm-only:
qemu/exec.c
void cpu_single_step(CPUState *cpu, int enabled)
{
if (cpu->singlestep_enabled != enabled) {
cpu->si
On 12/06/2019 23:34, Fabiano Rosas wrote:
> Alexey Kardashevskiy writes:
>
>> Are you reposting this any time soon?
>
> I have sent a v2 to the kernel side of it:
>
> https://lore.kernel.org/kvm/2019052919.27994-1-faro...@linux.ibm.com/
>
> I'm depending on what we decide to do there. T
Alexey Kardashevskiy writes:
> Are you reposting this any time soon?
I have sent a v2 to the kernel side of it:
https://lore.kernel.org/kvm/2019052919.27994-1-faro...@linux.ibm.com/
I'm depending on what we decide to do there. The core of this patchset
will not change, just the mechanism b
Are you reposting this any time soon?
In meanwhile I hit a problem when I cannot step over the "stdu" instruction.
I basically put this:
stdur1,-368(r1)
and "ni" in gdb does not stop on the next instruction which is quite
confusing. Ideas?
On 20/03/2019 12:42, Alexey Kardashevskiy wrote:
>
On 20/03/2019 01:32, Fabiano Rosas wrote:
> Alexey Kardashevskiy writes:
>
>> Looks good to me, does not break what already works. However I cannot
>> debug SLOF real mode and I am not sure why.
>>
>> (gdb) set endian big
>>
>> The target is assumed to be big endian
>> (gdb) b *0x3f00
>>
>> Br
Alexey Kardashevskiy writes:
> Looks good to me, does not break what already works. However I cannot
> debug SLOF real mode and I am not sure why.
>
> (gdb) set endian big
>
> The target is assumed to be big endian
> (gdb) b *0x3f00
>
> Breakpoint 2 at 0x3f00
I think I'm missing the point here.
On 01/03/2019 09:57, Fabiano Rosas wrote:
> The hardware singlestep mechanism in POWER works via a Trace Interrupt
> (0xd00) that happens after any instruction executes, whenever MSR_SE =
> 1 (PowerISA Section 6.5.15 - Trace Interrupt).
>
> However, with kvm_hv, the Trace Interrupt happens insi
The hardware singlestep mechanism in POWER works via a Trace Interrupt
(0xd00) that happens after any instruction executes, whenever MSR_SE =
1 (PowerISA Section 6.5.15 - Trace Interrupt).
However, with kvm_hv, the Trace Interrupt happens inside the guest and
KVM has no visibility of it. Therefore
