Richard Henderson writes:
> On 06/22/2016 09:25 AM, Alex Bennée wrote:
>>
>> Pranith Kumar writes:
>>
>>> Generate mfence/sfence/lfence instruction on SSE2 enabled
>>> processors. For older processors, generate a 'lock orl $0,0(%esp)'
>>> instruction
On 06/22/2016 09:25 AM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> Generate mfence/sfence/lfence instruction on SSE2 enabled
>> processors. For older processors, generate a 'lock orl $0,0(%esp)'
>> instruction which has full ordering semantics.
>>
>> Signed-off-by:
Pranith Kumar writes:
> Generate mfence/sfence/lfence instruction on SSE2 enabled
> processors. For older processors, generate a 'lock orl $0,0(%esp)'
> instruction which has full ordering semantics.
>
> Signed-off-by: Pranith Kumar
> [rth: Check
On 18/06/2016 06:03, Pranith Kumar wrote:
> Generate mfence/sfence/lfence instruction on SSE2 enabled
> processors. For older processors, generate a 'lock orl $0,0(%esp)'
> instruction which has full ordering semantics.
>
> Signed-off-by: Pranith Kumar
> [rth: Check for
Generate mfence/sfence/lfence instruction on SSE2 enabled
processors. For older processors, generate a 'lock orl $0,0(%esp)'
instruction which has full ordering semantics.
Signed-off-by: Pranith Kumar
[rth: Check for sse2, fallback to locked memory op otherwise.]