>On Mon, Aug 27, 2018 at 11:17:49PM +0800, peng.h...@zte.com.cn wrote: >> >On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.h...@zte.com.cn wrote:
>> >> > >> >> >Is there a reason to not register this port as coalesced PIO also for >> >> >Q35? >> >> >In q35_host_realize()? >> >> >If not, I would do that as an extra patch as part of this series. >> >> Just as I mentioned in patch [0/4] , you can add pci- >>>>host config port as coalesecd pio. I think it works for q35 port 0xcf8. >> >> >-Liran >> > >> >What's the performance improvement for q35? >> q35 also has the same pci-host config port 0xcf8 as piix. I test the >> coalesced pio for >> q35 pci-host config port 0xcf8. It spent less VM-exit avg time from 3us to >> 0.6us. >so pls include that patch too. piix is mostly feature frozen, piix only >features aren't likely to be merged. Hi, Liran，do you want to add the patch about q35 ?
