On 12/02/2015 22:57, Peter Maydell wrote:
The only
requirement is that if the CPU that did the TLB maintenance
op executes a DMB (barrier) then the TLB op must finish
before the barrier completes execution. So you could split
the kick off TLB invalidate and make sure all CPUs
are done
On 13/02/2015 10:37, Mark Burton wrote:
the memory barrier is on the cpu requesting the flush isn’t it (not
on the CPU that is being flushed)?
Oops, I misread Peter's explanation.
In that case, perhaps DMB can be treated in a similar way as WFI, using
cpu-halted. Queueing work on other CPUs
the memory barrier is on the cpu requesting the flush isn’t it (not on the CPU
that is being flushed)?
Cheers
Mark.
On 13 Feb 2015, at 10:34, Paolo Bonzini pbonz...@redhat.com wrote:
On 12/02/2015 22:57, Peter Maydell wrote:
The only
requirement is that if the CPU that did the TLB
Mark Burton writes:
On 13 Feb 2015, at 08:24, Peter Maydell peter.mayd...@linaro.org wrote:
On 13 February 2015 at 07:16, Mark Burton mark.bur...@greensocs.com wrote:
If the kernel is doing this - then effectively - for X86, each CPU only
flush’s it’s own TLB (from the perspective of Qemu)
Agreed
Cheers
Mark.
On 13 Feb 2015, at 14:30, Lluís Vilanova vilan...@ac.upc.edu wrote:
Mark Burton writes:
On 13 Feb 2015, at 08:24, Peter Maydell peter.mayd...@linaro.org wrote:
On 13 February 2015 at 07:16, Mark Burton mark.bur...@greensocs.com wrote:
If the kernel is doing this -
On 12 Feb 2015, at 16:31, Dr. David Alan Gilbert dgilb...@redhat.com wrote:
* Mark Burton (mark.bur...@greensocs.com) wrote:
On 12 Feb 2015, at 16:01, Peter Maydell peter.mayd...@linaro.org wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
On 12.02.2015, at
On 12 February 2015 at 15:19, Alexander Graf ag...@suse.de wrote:
On 12.02.15 16:08, Mark Burton wrote:
Our question is - do we need this ‘sync’ (before the flush),
or can we actually allow CPU’s to flush themselves asynchronously….
The respective target architecture specs will tell you. And
Mark Burton writes:
On 12 Feb 2015, at 16:38, Alexander Graf ag...@suse.de wrote:
On 12.02.15 15:58, Peter Maydell wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
almost nobody except x86 does global flushes
All ARM TLB maintenance operations have both this
On 12 February 2015 at 15:38, Alexander Graf ag...@suse.de wrote:
On 12.02.15 15:58, Peter Maydell wrote:
All ARM TLB maintenance operations have both this CPU only
and all TLBs in the Inner Shareable domain [that's ARM-speak
for every CPU core in the cluster] variants (the latter
being the
Up top - thanks Peter, I think you may give us an idea !
On 12 Feb 2015, at 23:10, Lluís Vilanova vilan...@ac.upc.edu wrote:
Mark Burton writes:
On 12 Feb 2015, at 16:38, Alexander Graf ag...@suse.de wrote:
On 12.02.15 15:58, Peter Maydell wrote:
On 12 February 2015 at 14:45,
On 13 Feb 2015, at 08:24, Peter Maydell peter.mayd...@linaro.org wrote:
On 13 February 2015 at 07:16, Mark Burton mark.bur...@greensocs.com wrote:
If the kernel is doing this - then effectively - for X86, each CPU only
flush’s it’s own TLB (from the perspective of Qemu) - correct?
(in
On 13 February 2015 at 07:16, Mark Burton mark.bur...@greensocs.com wrote:
If the kernel is doing this - then effectively - for X86, each CPU only
flush’s it’s own TLB (from the perspective of Qemu) - correct?
(in which case, for Qemu itself - for x86) - we dont need to implement
a global
On 12.02.2015, at 15:35, Mark Burton mark.bur...@greensocs.com wrote:
TLB Flush:
We have spent a few days on this issue, and still haven’t resolved the best
path.
Our solution seems to work, most of the time, but we still have some strange
issues - so I want to check that what we
TLB Flush:
We have spent a few days on this issue, and still haven’t resolved the best
path.
Our solution seems to work, most of the time, but we still have some strange
issues - so I want to check that what we are proposing has a chance of working.
Our plan is to allow all CPU’s to
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
On 12.02.2015, at 15:35, Mark Burton mark.bur...@greensocs.com wrote:
We are proposing to implement this by signalling all other CPU’s
to exit (and requesting they flush before re-starting). In other
words, this would happen
OK - Alex - your implication is that it has to be atomic, we need the sync…
:-(
I have a horrid feeling that the atomicity of global flush can’t be causing the
(almost, but not quite reproducible) errors we’re seeing - but… anyway ;-)
Cheers
Mark.
On 12 Feb 2015, at 15:45, Alexander
On 12.02.15 16:08, Mark Burton wrote:
On 12 Feb 2015, at 16:01, Peter Maydell peter.mayd...@linaro.org wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
On 12.02.2015, at 15:35, Mark Burton mark.bur...@greensocs.com wrote:
We are proposing to implement this by
* Mark Burton (mark.bur...@greensocs.com) wrote:
On 12 Feb 2015, at 16:01, Peter Maydell peter.mayd...@linaro.org wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
On 12.02.2015, at 15:35, Mark Burton mark.bur...@greensocs.com wrote:
We are proposing to
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
almost nobody except x86 does global flushes
All ARM TLB maintenance operations have both this CPU only
and all TLBs in the Inner Shareable domain [that's ARM-speak
for every CPU core in the cluster] variants (the latter
being the
On 12 Feb 2015, at 16:01, Peter Maydell peter.mayd...@linaro.org wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
On 12.02.2015, at 15:35, Mark Burton mark.bur...@greensocs.com wrote:
We are proposing to implement this by signalling all other CPU’s
to exit (and
On 12.02.15 15:58, Peter Maydell wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
almost nobody except x86 does global flushes
All ARM TLB maintenance operations have both this CPU only
and all TLBs in the Inner Shareable domain [that's ARM-speak
for every CPU core
On 12 Feb 2015, at 16:38, Alexander Graf ag...@suse.de wrote:
On 12.02.15 15:58, Peter Maydell wrote:
On 12 February 2015 at 14:45, Alexander Graf ag...@suse.de wrote:
almost nobody except x86 does global flushes
All ARM TLB maintenance operations have both this CPU only
and all
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