Right now the ne2000.c code claims that it emulates a RTL8029AS. It
does a very good job of that. However, the RTL8029 has a few
registers that are extensions to the NE-2000 design. None of these
registers are implemented. This can cause some confusion for those
drivers that assume that if the PCI ID says it is a RTL8029, it can
use the extra registers to set the media type and status. The patches
return the ID registers in the nic space as a real 8029 would, as well
as hard-wiring the configuration registers to 10baseT full duplex.
FreeBSD's ed driver is what got shot down by this lack of support.
When I added support for RTL80x9 chips recently, I broke support for
qemu inadvertantly (there were also some bugs in the support I added,
which I've since corrected). With these patches, the driver is happy
with qemu again, and reports it being a RTL8029. I've patched the
driver to cope with the ID registers not being correct by falling back
to a plain NE-2000 and not using the extra registers for media status.
In the interest of accuracy of emulation, I hope that you consider
these patches. You may include them in any future versions, if you
choose to, under any license that you see fit to use.
qemu rocks!
Warner
--- hw/ne2000.c~ Thu Oct 13 16:33:39 2005
+++ hw/ne2000.c Thu Oct 13 16:33:47 2005
@@ -47,7 +47,9 @@
#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
+#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
+#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
#define EN0_RSR 0x0c /* rx status reg RD */
#define EN0_RXCR 0x0c /* RX configuration reg WR */
#define EN0_TXCR 0x0d /* TX configuration reg WR */
@@ -64,6 +66,11 @@
#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
+#define EN3_CONFIG0 0x33
+#define EN3_CONFIG1 0x34
+#define EN3_CONFIG2 0x35
+#define EN3_CONFIG3 0x36
+
/* Register accessed at EN_CMD, the 8390 base addr. */
#define E8390_STOP 0x01 /* Stop and reset the chip */
#define E8390_START 0x02 /* Start the chip, clear reset */
@@ -385,6 +392,21 @@
case EN2_STOPPG:
ret = s->stop >> 8;
break;
+ case EN0_RTL8029ID0:
+ ret = 0x50;
+ break;
+ case EN0_RTL8029ID1:
+ ret = 0x43;
+ break;
+ case EN3_CONFIG0:
+ ret = 0; /* 10baseT media */
+ break;
+ case EN3_CONFIG2:
+ ret = 0x40; /* 10baseT active */
+ break;
+ case EN3_CONFIG3:
+ ret = 0x40; /* Full duplex */
+ break;
default:
ret = 0x00;
break;
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