On Mon, Oct 18, 2010 at 09:08:09AM +0200, Michael S. Tsirkin wrote:
> > The spec says the lower bits are read-only and they have its meaning.
>
> Yes. but my question is why even touch io base/io limit at all
> in this function?
> It looks like guest can not rely on these being 0 after reset.
Oh
On Mon, Oct 18, 2010 at 04:10:17PM +0900, Isaku Yamahata wrote:
> On Mon, Oct 18, 2010 at 08:22:24AM +0200, Michael S. Tsirkin wrote:
> > On Mon, Oct 18, 2010 at 12:17:46PM +0900, Isaku Yamahata wrote:
> > > lower 4bits of base/limit register is RO, and
> > > should not be modified on reset.
> > >
On Mon, Oct 18, 2010 at 08:22:24AM +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 18, 2010 at 12:17:46PM +0900, Isaku Yamahata wrote:
> > lower 4bits of base/limit register is RO, and
> > should not be modified on reset.
> >
> > Signed-off-by: Isaku Yamahata
> > ---
> > hw/pci_bridge.c | 15 ++
On Mon, Oct 18, 2010 at 12:17:46PM +0900, Isaku Yamahata wrote:
> lower 4bits of base/limit register is RO, and
> should not be modified on reset.
>
> Signed-off-by: Isaku Yamahata
> ---
> hw/pci_bridge.c | 15 +--
> 1 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git
