Forget this. My test was flawed because I still wasn't comparing apples
to apples. I was comparing the pre-bootloader state to the
post-bootloader state, and it seems that OBP, even on a real machine,
shows all the registers as zero before it runs any program.
However, I still think there's some
Blue Swirl wrote:
> On Sun, Dec 12, 2010 at 12:17 AM, Bob Breuer wrote:
>
>> Under qemu-system-sparc, I found a problem with OBP's psr commands.
>>
>> On an real SS-20, I get:
>>ok .psr
>>CWP: 4 ET: 1 PS: 1 S: 1 PIL: f EF: 1 EC: 0 ICC: nZvc VER: 0
>> IMPL: 4
>>ok %psr .
>>
On Sun, Dec 12, 2010 at 12:17 AM, Bob Breuer wrote:
> Under qemu-system-sparc, I found a problem with OBP's psr commands.
>
> On an real SS-20, I get:
> ok .psr
> CWP: 4 ET: 1 PS: 1 S: 1 PIL: f EF: 1 EC: 0 ICC: nZvc VER: 0
> IMPL: 4
> ok %psr .
> 40401fe4
> But with qemu, it al
