MIPS64R2-generic implements the MIPS-3D ASE, so I assume it should also have a 64-bit FPU. Please apply if OK.
Richard
Index: target-mips/translate_init.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v retrieving revision 1.35 diff -u -p -r1.35 translate_init.c --- target-mips/translate_init.c 25 Dec 2007 20:46:56 -0000 1.35 +++ target-mips/translate_init.c 28 Dec 2007 11:24:55 -0000 @@ -403,9 +403,9 @@ static mips_def_t mips_defs[] = .SYNCI_Step = 32, .CCRes = 2, .CP0_Status_rw_bitmask = 0x36FBFFFF, - .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) | - (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | - (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), .SEGBITS = 42, /* The architectural limit is 59, but we have hardcoded 36 bit in some places...