Re: [Qemu-devel] target-ppc: Fix SRR0 when taking unaligned exceptions

2015-08-26 Thread Alexander Graf
On 02.07.15 06:44, Anton Blanchard wrote: > We are setting SRR0 to the instruction before the one causing the > unaligned exception. A quick testcase: > > . = 0x100 > .globl _start > _start: > /* Cause a 0x600 */ > li 3,0x1 > stwcx. 3,0,3 > 1:b 1b > > . = 0x600

[Qemu-devel] target-ppc: Fix SRR0 when taking unaligned exceptions

2015-07-01 Thread Anton Blanchard
We are setting SRR0 to the instruction before the one causing the unaligned exception. A quick testcase: . = 0x100 .globl _start _start: /* Cause a 0x600 */ li 3,0x1 stwcx. 3,0,3 1: b 1b . = 0x600 1: b 1b Built into something we can load as a B