Hi Alistair,
On Wed, Oct 28, 2020 at 1:42 AM Alistair Francis wrote:
>
> On Tue, Oct 27, 2020 at 7:53 AM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > Somehow HSS needs to access address 0 [1] for the DDR calibration data
> > which is in the chipset's debug memory. Let's map the debug memory.
On Tue, Oct 27, 2020 at 7:53 AM Bin Meng wrote:
>
> From: Bin Meng
>
> Somehow HSS needs to access address 0 [1] for the DDR calibration data
> which is in the chipset's debug memory. Let's map the debug memory.
>
> [1] See the config_copy() calls in various places in ddr_setup() in
> the HSS
From: Bin Meng
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's debug memory. Let's map the debug memory.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng
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hw/riscv/microch
