Re: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write

On Wed, Jan 19, 2022 at 11:06 AM Alistair Francis wrote: > > On Wed, Jan 5, 2022 at 1:15 PM Bin Meng wrote: > > > > From: Bin Meng > > > > This adds debug CSR read/write support to the RISC-V CSR RW table. > > > > Signed-off-by: Bin Meng > > --- > > > > Changes in v3: > > - add riscv_trigger_in

Re: [RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write

On Wed, Jan 5, 2022 at 1:15 PM Bin Meng wrote: > > From: Bin Meng > > This adds debug CSR read/write support to the RISC-V CSR RW table. > > Signed-off-by: Bin Meng > --- > > Changes in v3: > - add riscv_trigger_init(), moved from patch #1 to this patch > > target/riscv/debug.h | 2 ++ > targe

[RESEND PATCH v3 5/7] target/riscv: csr: Hook debug CSR read/write

From: Bin Meng This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng --- Changes in v3: - add riscv_trigger_init(), moved from patch #1 to this patch target/riscv/debug.h | 2 ++ target/riscv/cpu.c | 6 + target/riscv/csr.c | 57