On Wed May 29, 2024 at 5:00 PM AEST, Cédric Le Goater wrote:
> On 5/26/24 14:26, Nicholas Piggin wrote:
> > The PC unit in the processor core contains xscom registers that provide
> > low level status and control of the CPU.
> >
> > This implements "direct controls" sufficient for OPAL (skiboot) f
On 5/26/24 14:26, Nicholas Piggin wrote:
The PC unit in the processor core contains xscom registers that provide
low level status and control of the CPU.
This implements "direct controls" sufficient for OPAL (skiboot) firmware
use, which is to stop threads and send them non-maskable IPIs in the
The PC unit in the processor core contains xscom registers that provide
low level status and control of the CPU.
This implements "direct controls" sufficient for OPAL (skiboot) firmware
use, which is to stop threads and send them non-maskable IPIs in the
form of SRESET interrupts.
POWER10 is suff
