On 2/27/23 21:44, gaosong wrote:
Hi, Richard
在 2023/2/25 上午7:01, Richard Henderson 写道:
On 2/23/23 21:24, gaosong wrote:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_w_h,
.opt_opc = vecop_list,
.vece = MO_32
},
On 2/27/23 17:30, gaosong wrote:
Vd->Q(0) = int128_add((Int128)Vj->D(0), (Int128)Vk->D(0));
You cannot cast like this.
You must use int128_make{64,s64}.
These ways are can be chosen?
Yes, out-of-line is a valid choice.
r~
Hi, Richard
在 2023/2/25 上午7:01, Richard Henderson 写道:
On 2/23/23 21:24, gaosong wrote:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_w_h,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv =
在 2023/2/28 上午2:40, Richard Henderson 写道:
On 2/27/23 02:55, gaosong wrote:
在 2023/2/25 上午3:24, Richard Henderson 写道:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_q_d,
.opt_opc = vecop_list,
.vece = MO_128
},
There
On 2/27/23 02:55, gaosong wrote:
在 2023/2/25 上午3:24, Richard Henderson 写道:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_q_d,
.opt_opc = vecop_list,
.vece = MO_128
},
There are no 128-bit vector operations; you'll
On 2/27/23 02:54, gaosong wrote:
在 2023/2/27 下午5:20, Richard Henderson 写道:
On 2/26/23 23:14, gaosong wrote:
like this:
the vece is MO_32.
static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t1 = tcg_temp_new_vec_matching(a);
TCGv_vec t2 =
在 2023/2/25 上午3:24, Richard Henderson 写道:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_q_d,
.opt_opc = vecop_list,
.vece = MO_128
},
There are no 128-bit vector operations; you'll need to do this one
differently.
在 2023/2/27 下午5:20, Richard Henderson 写道:
On 2/26/23 23:14, gaosong wrote:
like this:
the vece is MO_32.
static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a,
TCGv_vec b)
{
TCGv_vec t1 = tcg_temp_new_vec_matching(a);
TCGv_vec t2 = tcg_temp_new_vec_matching(b);
int
On 2/26/23 23:14, gaosong wrote:
like this:
the vece is MO_32.
static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t1 = tcg_temp_new_vec_matching(a);
TCGv_vec t2 = tcg_temp_new_vec_matching(b);
int halfbits = 4 << vece;
在 2023/2/25 上午3:24, Richard Henderson 写道:
On 2/23/23 21:24, gaosong wrote:
I was wrong, the instruction is to sign-extend the odd or even
elements of the vector before the operation, not to sign-extend the
result.
E.g
vaddwev_h_b vd, vj, vk
vd->H[i] = SignExtend(vj->B[2i]) +
On 2/23/23 21:24, gaosong wrote:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_w_h,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_d_w,
On 2/23/23 21:24, gaosong wrote:
I was wrong, the instruction is to sign-extend the odd or even elements of the vector
before the operation, not to sign-extend the result.
E.g
vaddwev_h_b vd, vj, vk
vd->H[i] = SignExtend(vj->B[2i]) + SignExtend(vk->B[2i]);
vaddwev_w_h vd, vj, vk
vd->W[i] =
在 2023/2/23 下午11:22, Richard Henderson 写道:
On 2/22/23 22:23, gaosong wrote:
Hi, Richard
在 2023/2/21 上午1:21, Richard Henderson 写道:
On 2/19/23 21:47, gaosong wrote:
I have some questions:
1 Should we need implement GVecGen* for simple gvec instructiosn?
such as add, sub , or , xor..
On 2/22/23 22:23, gaosong wrote:
Hi, Richard
在 2023/2/21 上午1:21, Richard Henderson 写道:
On 2/19/23 21:47, gaosong wrote:
I have some questions:
1 Should we need implement GVecGen* for simple gvec instructiosn?
such as add, sub , or , xor..
No, these are done generically.
2 Should we
Hi, Richard
在 2023/2/21 上午1:21, Richard Henderson 写道:
On 2/19/23 21:47, gaosong wrote:
I have some questions:
1 Should we need implement GVecGen* for simple gvec instructiosn?
such as add, sub , or , xor..
No, these are done generically.
2 Should we need implement all fni8/fni4,
On 2/19/23 21:47, gaosong wrote:
I have some questions:
1 Should we need implement GVecGen* for simple gvec instructiosn?
such as add, sub , or , xor..
No, these are done generically.
2 Should we need implement all fni8/fni4, fniv, fno?
You need not implement them all. Generally
Hi, Richard
在 2022/12/25 上午1:48, Richard Henderson 写道:
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vaddwev_h_b, gen_vvv, gen_helper_vaddwev_h_b)
+TRANS(vaddwev_w_h, gen_vvv, gen_helper_vaddwev_w_h)
+TRANS(vaddwev_d_w, gen_vvv, gen_helper_vaddwev_d_w)
+TRANS(vaddwev_q_d, gen_vvv,
On 12/24/22 00:16, Song Gao wrote:
+TRANS(vaddwev_h_b, gen_vvv, gen_helper_vaddwev_h_b)
+TRANS(vaddwev_w_h, gen_vvv, gen_helper_vaddwev_w_h)
+TRANS(vaddwev_d_w, gen_vvv, gen_helper_vaddwev_d_w)
+TRANS(vaddwev_q_d, gen_vvv, gen_helper_vaddwev_q_d)
+TRANS(vaddwod_h_b, gen_vvv,
This patch includes:
- VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/disas.c| 43
target/loongarch/helper.h | 43
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