On Mon, Jun 07, 2021 at 01:54:15PM -0300, Fabiano Rosas wrote:
> David Gibson writes:
>
> > On Tue, Jun 01, 2021 at 06:46:49PM -0300, Fabiano Rosas wrote:
> >> +typedef void (*ppc_intr_fn_t)(PowerPCCPU *cpu, PPCInterrupt *intr,
> >> + int excp_model, ppc_intr_args *re
David Gibson writes:
> On Tue, Jun 01, 2021 at 06:46:49PM -0300, Fabiano Rosas wrote:
>> +typedef void (*ppc_intr_fn_t)(PowerPCCPU *cpu, PPCInterrupt *intr,
>> + int excp_model, ppc_intr_args *regs,
>> + bool *ignore);
>
> Hmm. Using this
On Tue, Jun 01, 2021 at 06:46:49PM -0300, Fabiano Rosas wrote:
> This patch introduces a new way to dispatch the emulated interrupts in
> powerpc_excp. It leverages the QEMU object model to store the
> implementations for each interrupt and link them to their identifier
> from POWERPC_EXCP enum. Th
Bruno Piazera Larsen writes:
> On 01/06/2021 18:46, Fabiano Rosas wrote:
>> +struct ppc_intr_args {
>> +target_ulong nip;
>> +target_ulong msr;
>> +target_ulong new_nip;
>> +target_ulong new_msr;
>> +int sprn_srr0;
>> +int sprn_srr1;
>> +int sprn_asrr0;
>> +int
On 01/06/2021 18:46, Fabiano Rosas wrote:
This patch introduces a new way to dispatch the emulated interrupts in
powerpc_excp. It leverages the QEMU object model to store the
implementations for each interrupt and link them to their identifier
from POWERPC_EXCP enum. The processor-specific code
This patch introduces a new way to dispatch the emulated interrupts in
powerpc_excp. It leverages the QEMU object model to store the
implementations for each interrupt and link them to their identifier
from POWERPC_EXCP enum. The processor-specific code then uses this
identifier to register which i
