On Tue, 21 Mar 2023 at 13:55, Mostafa Saleh wrote:
>
> Hi Peter,
>
> On Tue, Mar 21, 2023 at 01:34:55PM +, Peter Maydell wrote:
> > > >>> + */
> > > >>> +ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> > > >>> +uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0,
> > > >>> ID_AA64MMFR
Hi Peter,
On Tue, Mar 21, 2023 at 01:34:55PM +, Peter Maydell wrote:
> > >>> + */
> > >>> +ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> > >>> +uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0, ID_AA64MMFR0,
> > >>> PARANGE);
> > >> is this working in accelerated mode?
> > > I di
Hi Peter,
On 3/21/23 14:34, Peter Maydell wrote:
> thout having read much of the context, but why
> would we need to migrate the ID registers? They are constant, read-only,
> so they will be the same value on both source and destination.
this series modifies the values of IDR[5] (oas). So my unde
Hi Peter,
On Tue, Mar 21, 2023 at 01:34:55PM +, Peter Maydell wrote:
> > >>> +s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, oas);
> > >> I am not sure you can change that easily. In case of migration this is
> > >> going to change the behavior of the device, no?
> > > I see IDR registers ar
On Tue, 21 Mar 2023 at 13:23, Eric Auger wrote:
>
> Hi Mostafa,
>
> On 3/21/23 14:06, Mostafa Saleh wrote:
> > Hi Eric,
> >
> >>> + * According to 6.3.6 SMMU_IDR5, OAS must match the system physical
> >>> address
> >>> + * size.
> >>> + */
> >>> +ARMCPU *armcpu = ARM_CPU(qemu_get_
On 3/21/23 14:29, Mostafa Saleh wrote:
> On Tue, Mar 21, 2023 at 02:23:03PM +0100, Eric Auger wrote:
> s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
> -s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44
> bits */
> +s->idr[5] = FIELD_DP32(s->i
On Tue, Mar 21, 2023 at 02:23:03PM +0100, Eric Auger wrote:
> >>> s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1);
> >>> -s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS); /* 44
> >>> bits */
> >>> +s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, oas);
> >> I am not sure y
Hi Mostafa,
On 3/21/23 14:06, Mostafa Saleh wrote:
> Hi Eric,
>
>>> + * According to 6.3.6 SMMU_IDR5, OAS must match the system physical
>>> address
>>> + * size.
>>> + */
>>> +ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
>>> +uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0,
Hi Eric,
> > + * According to 6.3.6 SMMU_IDR5, OAS must match the system physical
> > address
> > + * size.
> > + */
> > +ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> > +uint8_t oas = FIELD_EX64(armcpu->isar.id_aa64mmfr0, ID_AA64MMFR0,
> > PARANGE);
> is this working in accel
Hi Mostafa,
On 2/26/23 23:06, Mostafa Saleh wrote:
> OAS used to be hardcoded to 44 bits, however according to SMMU manual
> 6.3.6 SMMU_IDR5, OAS must match the system physical address size, so
> we read it from CPU PARANGE.
>
> Remove PA_MAX and pa_range as they were not used.
>
> Add SMMUv3State
OAS used to be hardcoded to 44 bits, however according to SMMU manual
6.3.6 SMMU_IDR5, OAS must match the system physical address size, so
we read it from CPU PARANGE.
Remove PA_MAX and pa_range as they were not used.
Add SMMUv3State as an argument to decode_cd, so it can read the SMMU
OAS.
As C
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