Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

On 6/3/24 10:50, Max Chou wrote: Hi Richart, Thank you for your feedback. This version is created by referencing the gen_sve_ldr translation function with the similar assumptions that no mask(predication)/no tail agnostic/continuous load & store. Except that gen_sve_ldr has a compile-time

Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

Hi Richart, Thank you for your feedback. This version is created by referencing the gen_sve_ldr translation function with the similar assumptions that no mask(predication)/no tail agnostic/continuous load & store. You are right, the expansion is large in this version (over 20 TCG instructions

Re: [RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

On 5/31/24 12:44, Max Chou wrote: The vector unit-stride load/store instructions (e.g. vle8.v/vse8.v) perform continuous load/store. We can replace the corresponding helper functions by TCG ops to copy more data at a time with following assumptions: * Perform virtual address resolution once for

[RFC PATCH v2 5/6] target/riscv: rvv: Optimize v[l|s]e8.v with limitations

The vector unit-stride load/store instructions (e.g. vle8.v/vse8.v) perform continuous load/store. We can replace the corresponding helper functions by TCG ops to copy more data at a time with following assumptions: * Perform virtual address resolution once for entire vector at beginning *