The simplified emulation of vector loads and stores that bypasses the memory probing in the vext_ldst_us helper function seem to benefit only the user mode. We therefore limit this approach to the user mode configuration.
Signed-off-by: Paolo Savini <paolo.sav...@embecosm.com> --- target/riscv/vector_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9026661573..08f71abc22 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -648,6 +648,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, VSTART_CHECK_EARLY_EXIT(env); +#ifdef CONFIG_USER_ONLY /* For data sizes <= 64 bits and for LMUL=1 with VLEN=128 bits we get a * better performance by doing a simple simulation of the load/store * without the overhead of prodding the host RAM */ @@ -692,7 +693,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems); return; } - +#endif vext_cont_ldst_elements(&info, base, env->vreg, env->vstart, evl, desc, log2_esz, false); -- 2.34.1