Re: [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction

On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote: > # Vector ordered and unordered reduction sum > -vfredsum_vs -1 . . . 001 . 1010111 @r_vm > +vfredsum_vs 01 . . . 001 . 1010111 @r_vm > +vfredosum_vs11 . . . 001 . 1010111 @r_vm "The vfr

[RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction

From: Frank Chang Separate the implementation of vfredsum.vs and vfredosum.vs. Introduce propagate NaN feature for vfredsum.vs as implementations are permitted to canonicalize the NaN and, if the NaN is signaling, set the invalid exception flag. Signed-off-by: Frank Chang --- target/riscv/hel