Richard Henderson writes:
> On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote:
>> +if (env->misa & RVV) {
>> +/* TODO: support vlen other than 128, 256, 512 bits. */
>> +const char *vector_xml_name = NULL;
>> +switch (cpu->cfg.vlen) {
>> +case 128:
>> +
On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote:
> +if (env->misa & RVV) {
> +/* TODO: support vlen other than 128, 256, 512 bits. */
> +const char *vector_xml_name = NULL;
> +switch (cpu->cfg.vlen) {
> +case 128:
> +vector_xml_name = "riscv-64bit-ve
From: Hsiangkai Wang
Signed-off-by: Hsiangkai Wang
Signed-off-by: Frank Chang
---
configure | 2 +-
gdb-xml/riscv-64bit-csr.xml | 7
gdb-xml/riscv-64bit-vector-128b.xml | 59 +++
gdb-xml/riscv-64bit-vector-256b.xml | 59 +
