Signed-off-by: Stephen Long <stepl...@quicinc.com>
---
sve2.risu | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/sve2.risu b/sve2.risu
index 6177848..adc5dd1 100755
--- a/sve2.risu
+++ b/sve2.risu
@@ -1,6 +1,19 @@
# Input file for risugen defining AArch64 SVE2 instructions
.mode arm.aarch64
+# Bitwise Shift (Unpredicated)
+## bitwise shift by immediate (predicated)
+SQSHL_imm A64_V 00000100 tszh:2 00 0110 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+UQSHL_imm A64_V 00000100 tszh:2 00 0111 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SRSHR A64_V 00000100 tszh:2 00 1100 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+URSHR A64_V 00000100 tszh:2 00 1101 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+SQSHLU A64_V 00000100 tszh:2 00 1111 100 pg:3 tszl:2 imm3:3 zdn:5 \
+!constraints { !($tszh == 0 && $tszl == 0); }
+
# Integer Multiply (Unpredicated)
## integer multiply vectors (unpredicated)
MUL A64_V 00000100 size:2 1 zm:5 0110 00 zn:5 zd:5
--
2.25.1
