On 6/18/21 4:17 PM, Alex Bennée wrote:
>
> Andrey Shinkevich writes:
>
>> Dear Shashi,
>>
>> I have applied the version 4 of the series "GICv3 LPI and ITS feature
>> implementation" right after the commit 3e9f48b as before (because the
>> GCCv7.5 is unavailable in the YUM repository for CentOS-7
Shinkevich writes:
>> >
>> >> Dear colleagues,
>> >>
>> >> I am looking for ways to accelerate the MTTCG for ARM guest on
>> x86-64 host.
>> >> The maximum number of CPUs for MTTCG that uses GICv2 is limited
On 6/17/21 8:44 PM, shashi.mall...@linaro.org wrote:
> Hi Andrey,
>
> The issue doesnt seem related to ITS patchset as the implementation has
> no changes around MTTCG or vCPU configurations.
>
> if this patchset were not applied(with only commit 3e9f48b),do you
> still see the hang issue?
No, I
't we? I will test it as well.
> >
> > Best regards,
> > Andrey Shinkevich
> >
> >
> > On 5/12/21 6:43 PM, Alex Bennée wrote:
> > >
> > > Andrey Shinkevich writes:
> > >
> > >> Dear colleagues,
>
> Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
> > Date: Thu, 29 Apr 2021 19:41:53 -0400
> > Message-Id: <20210429234201.125565-1-shashi.mall...@linaro.org>
> >
> > please do review and test.
> >
>
(ITS)
>>>> for using by MTTCG for ARM architecture.
>>>
>>> There is some work to support ITS under TCG already posted:
>>>
>>> Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
>>> Date: Thu, 29 Apr 2021 19:41:53 -0400
slation Service (ITS)
>>>> for using by MTTCG for ARM architecture.
>>>
>>> There is some work to support ITS under TCG already posted:
>>>
>>> Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
>>> Date: Thu, 29 Apr 2021
architecture.
> >
> > There is some work to support ITS under TCG already posted:
> >
> > Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
> > Date: Thu, 29 Apr 2021 19:41:53 -0400
> > Message-Id: <20210
;>
>>Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
>> Date: Thu, 29 Apr 2021 19:41:53 -0400
>>Message-Id: <20210429234201.125565-1-shashi.mall...@linaro.org>
>>
>> please do review and test.
>>
>>> Do you find that
e is some work to support ITS under TCG already posted:
> >
> > Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
> > Date: Thu, 29 Apr 2021 19:41:53 -0400
> > Message-Id: <20210429234201.125565-1-shashi.mall...@linaro.org>
> >
> >
r TCG already posted:
>
>Subject: [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
>Date: Thu, 29 Apr 2021 19:41:53 -0400
>Message-Id: <20210429234201.125565-1-shashi.mall...@linaro.org>
>
> please do review and test.
>
>> Do you find that idea u
9234201.125565-1-shashi.mall...@linaro.org>
please do review and test.
> Do you find that idea useful and feasible?
> If yes, how much time do you estimate for such a project to complete by
> one developer?
> If no, what are reasons for not implementing GICv3 for MTTCG in QEMU?
As f
ARM architecture.
Do you find that idea useful and feasible?
If yes, how much time do you estimate for such a project to complete by
one developer?
If no, what are reasons for not implementing GICv3 for MTTCG in QEMU?
Are you looking for something like that [*]? I think it has been on the
list for
feasible?
If yes, how much time do you estimate for such a project to complete by
one developer?
If no, what are reasons for not implementing GICv3 for MTTCG in QEMU?
Best regards,
Andrey Shinkevich
On 5/11/21 12:51 PM, Andrey Shinkevich wrote:
The version 3 of the Generic Interrupt Controller (GICv3) is not
supported in QEMU for some reason unknown to me.
It is supported. You have to enable it like so:
-M virt,gic-version=3
r~
15 matches
Mail list logo
