J. Mayer wrote:
No. Since MIPS{32,64}R2 the CP0 is standardized and a mandatory part of
a MIPS compatible CPU.
Yes, I know MIPS want always CP0 to be present. I should have put a
smiley somewhere. I wanted just to point the fact that the CPU itself
does not need the CP0 controller to run
On Sun, 2007-04-08 at 01:04 +0100, Thiemo Seufer wrote:
J. Mayer wrote:
[snip]
To give you an real example why arbitrary limits are not acceptable AT
ALL: I know an embedded Mips device (widely used !) with 2 CPU, 8 PIC
and about 500 IRQ sources.
Care to tell which one this is?
I'm
On Sun, 2007-04-08 at 09:49 +0200, J. Mayer wrote:
I'm sorry, I'm no sure I can (NDA rules).
Let's say it's a chips used in some consumer electronics products.
I gave this example to show that we cannot pre-determine any limit to
the number of PINs we have to manage, even if it's a poor
J. Mayer wrote:
On Sun, 2007-04-08 at 01:04 +0100, Thiemo Seufer wrote:
J. Mayer wrote:
[snip]
To give you an real example why arbitrary limits are not acceptable AT
ALL: I know an embedded Mips device (widely used !) with 2 CPU, 8 PIC
and about 500 IRQ sources.
Care to tell
On Sun, 2007-04-08 at 15:41 +0100, Thiemo Seufer wrote:
J. Mayer wrote:
On Sun, 2007-04-08 at 01:04 +0100, Thiemo Seufer wrote:
J. Mayer wrote:
[snip]
To give you an real example why arbitrary limits are not acceptable AT
ALL: I know an embedded Mips device (widely used !) with 2
