Hi Cedric,
> Subject: Re: [PATCH v2 06/11] hw/i2c/aspeed: support Tx/Rx buffer 64 bits
> address
>
> Jamin,
>
> Please change commit title to
>
Thanks for review and suggestion.
Will fix them in v3 patch.
Jamin
>hw/i2c/aspeed: Add support for Tx/Rx buffer 64 b
Jamin,
Please change commit title to
hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bits address
So more proposals to improve the commit log below,
On 8/8/24 04:49, Jamin Lin wrote:
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " wh
