> >>
> > Hi Cedrice,
> >
> > Thanks for review and sorry reply you late.
> >
> >> On 3/4/24 10:29, Jamin Lin wrote:
> >>> The SDRAM memory controller(DRAMC) controls the access to external
> >>> DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
> >>>
> >>> The DRAM memory controller of AST2700
: Re: [PATCH v2 3/9] aspeed/sdmc: Add AST2700 support
Hi Cedrice,
Thanks for review and sorry reply you late.
On 3/4/24 10:29, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory
>
> Subject: Re: [PATCH v2 3/9] aspeed/sdmc: Add AST2700 support
>
Hi Cedrice,
Thanks for review and sorry reply you late.
> On 3/4/24 10:29, Jamin Lin wrote:
> > The SDRAM memory controller(DRAMC) controls the access to external
> > DDR4 and DDR5 SDRAM and power up to DD
On 3/4/24 10:29, Jamin Lin wrote:
The SDRAM memory controller(DRAMC) controls the access to external
DDR4 and DDR5 SDRAM and power up to DDR4 and DDR5 PHY.
The DRAM memory controller of AST2700 is not backward compatible
to previous chips such AST2600, AST2500 and AST2400.
Max memory is now 8Gi
