Hi peter:
i see, much, much helpfull. thank you! :).
At 2024-04-09 18:51:26, "Peter Maydell" wrote:
>On Tue, 9 Apr 2024 at 11:40, tugouxp <13824125...@163.com> wrote:
>> ===>yes, i somehow a little bit of guess such like that, but when try to
>> find some code in qemu to prove the guess, i f
On Tue, 9 Apr 2024 at 11:40, tugouxp <13824125...@163.com> wrote:
> ===>yes, i somehow a little bit of guess such like that, but when try to find
> some code in qemu to prove the guess, i found i was lost and exausted in the
> ocean of the code and complex logic of qeumu.
> because in my thougth,
Hi peter;
much, much appreciate your explanation!
> ..but the host doesn't have one, we arrange to pause execution of all the
> other guest vCPU threads,
===>yes, i somehow a little bit of guess such like that, but when try to find
some code in qemu to prove the guess, i found i was lost and
On Tue, 9 Apr 2024 at 10:58, tugouxp <13824125...@163.com> wrote:
>How does the qemu emulate the target that support "atomic" ISA, such as
> riscv "amo" instruction on host machine that does NOT support atomic
> instructions ?
> is this scenario happends?
All hosts that can run QEMU support
Hi folks:
How does the qemu emulate the target that support "atomic" ISA, such as
riscv "amo" instruction on host machine that does NOT support atomic
instructions ?
is this scenario happends?
thank you!
BRs
zlcao.
