re).
> Was this issue addressed, or does it remain unfixed? I remember
> seeing x86 FPU patches merged recently, but I don't know if they
> were related to this.
>
I haven't done anything to address this issue.
>>> Robert Henry
>>>
te the correct
> hardware behavior?
>
> If possible add a test case to tests/tcg/i386/test-i386.c (see
> test_fxsave there).
Was this issue addressed, or does it remain unfixed? I remember
seeing x86 FPU patches merged recently, but I don't know if they
were related to this.
>
e behavior?
If possible add a test case to tests/tcg/i386/test-i386.c (see
test_fxsave there).
>
> Robert Henry
> ----------------
> *From:* Robert Henry
> *Sent:* Friday, May 29, 2020 10:38 AM
> *To:* qemu-devel@nongnu
ssing something?
Robert Henry
From: Robert Henry
Sent: Friday, May 29, 2020 10:38 AM
To: qemu-devel@nongnu.org
Subject: ia-32/ia-64 fxsave64 instruction behavior when saving mmx
Background: The ia-32/ia-64 fxsave64 instruction saves fp80 or legacy SSE mmx
registers.
Background: The ia-32/ia-64 fxsave64 instruction saves fp80 or legacy SSE mmx
registers. The mmx registers are saved as if they were fp80 values. The lower
64 bits of the constructed fp80 value is the mmx register. The upper 16 bits
of the constructed fp80 value are reserved; see the last row o
