Re: [Qemu-devel] [PULL 00/24] target-arm queue

nch 'remotes/juanquintela/tags/migration/20180115' > into staging (2018-01-15 13:17:47 +) > > are available in the git repository at: > > git://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20180116 > > for you to fetch changes up to 60765b6ceeb

Re: [Qemu-devel] [PULL v3 00/53] Misc changes for 2017-01-12

On 16 January 2018 at 14:26, Paolo Bonzini wrote: > On 16/01/2018 15:22, Marc-André Lureau wrote: >>> * if not, and assuming --enable-debug tries to enable ASAN, should >>> --enable-debug complain if fiber support is not required? Should >>> --enable-debug enable ASAN if

[Qemu-devel] [PATCH 1/3] exynos4210: workaround UBSAN compilation error

gcc 5.4.0-6ubuntu1~16.04.5 build with UBSAN enabled error: CC hw/display/exynos4210_fimd.o /home/petmay01/linaro/qemu-for-merges/hw/display/exynos4210_fimd.c: In function ‘fimd_get_buffer_id’: /home/petmay01/linaro/qemu-for-merges/hw/display/exynos4210_fimd.c:1105:5: error: case label does

[Qemu-devel] [PATCH v2 2/4] acpi: build QEMU table for PPI virtual memory device

To avoid having to hard code the base address of the PPI virtual memory device we introduce a QEMU ACPI table that holds the base address, if a TPM 1.2 or 2 is used. This table gives us flexibility to move the base address later on. Signed-off-by: Stefan Berger ---

[Qemu-devel] [PATCH v2 4/4] acpi: build TPM Physical Presence interface

The TPM Physical Presence interface consists of an ACPI part, a shared memory part, and code in the firmware. Users can send messages to the firmware by writing a code into the shared memory through invoking the ACPI code. When a reboot happens, the firmware looks for the code and acts on it by

[Qemu-devel] [PATCH v2 1/4] tpm: implement virtual memory device for TPM PPI

Implement a virtual memory device for the TPM Physical Presence interface. The memory is located at 0xfffef000 and used by ACPI to send messages to the firmware (BIOS) and by the firmware to provide parameters for each one of the supported codes. This device should be used by all TPM interfaces

Re: [Qemu-devel] [RFC PATCH 0/3] vfio: ccw: basic channel path event handling

On Tue, 16 Jan 2018 11:16:27 +0800 Dong Jia Shi wrote: > * Pierre Morel [2018-01-15 11:21:47 +0100]: > > > On 15/01/2018 09:57, Dong Jia Shi wrote: > > >* Cornelia Huck [2018-01-11 11:54:22 +0100]: > > > > > >>On

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 3/8] s390-ccw: parse and set boot menu options

On 01/16/2018 07:44 AM, Thomas Huth wrote: On 15.01.2018 17:44, Collin L. Walling wrote: Set boot menu options for an s390 guest and store them in the iplb. These options are set via the QEMU command line option: -boot menu=on|off[,splash-time=X] or via the libvirt domain xml:

Re: [Qemu-devel] [PULL 08/51] chardev: introduce qemu_chr_timeout_add_ms()

On 16/01/2018 15:43, Daniel P. Berrange wrote: >> >> It's a replacement of g_timeout_add[_seconds]() for chardevs. Chardevs >> now can have dedicated gcontext, we should always bind chardev tasks >> onto those gcontext rather than the default main context. Since there >> are quite a few of

[Qemu-devel] [PATCH 3/3] ucontext: annotate coroutine stack for ASAN

It helps ASAN to detect more leaks on coroutine stacks, and to get rid of some extra warnings. Before: tests/test-coroutine -p /basic/lifecycle /basic/lifecycle: ==20781==WARNING: ASan doesn't fully support makecontext/swapcontext functions and may produce false positives in some cases!

[Qemu-devel] [PATCH v2 3/4] acpi: implement aml_lless_equal

LLessEqualOp = LNotOp LGreaterOp Signed-off-by: Stefan Berger Reviewed-by: Marc-André Lureau Reviewed-by: Igor Mammedov --- hw/acpi/aml-build.c | 11 +++ include/hw/acpi/aml-build.h | 1 + 2 files

Re: [Qemu-devel] [PATCH v2 3/4] acpi: implement aml_lless_equal

On Tue, Jan 16, 2018 at 10:51:39AM -0500, Stefan Berger wrote: > LLessEqualOp = LNotOp LGreaterOp > > Signed-off-by: Stefan Berger > Reviewed-by: Marc-André Lureau > Reviewed-by: Igor Mammedov Reviewed-by: Michael

Re: [Qemu-devel] [PULL v1 0/8] Xilinx queue

On Tue, Jan 16, 2018 at 02:17:04PM +, Peter Maydell wrote: > On 16 January 2018 at 11:50, Edgar E. Iglesias > wrote: > > From: "Edgar E. Iglesias" > > > > The following changes since commit f5213bd060b460c99e605472b7e03967db43: > > >

Re: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit

> -Original Message- > From: Eduardo Habkost [mailto:ehabk...@redhat.com] > Sent: Monday, January 15, 2018 8:23 PM > To: Gonglei (Arei) > Cc: qemu-devel@nongnu.org; Paolo Bonzini > Subject: Re: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit > > On Sat, Jan 13, 2018 at 03:04:44AM

Re: [Qemu-devel] [PATCH 2/4] vhost-user: specify and implement VHOST_USER_SET_QUEUE_NUM request

On 01/16/2018 04:05 AM, Michael S. Tsirkin wrote: On Fri, Jan 12, 2018 at 03:56:56PM +0100, Maxime Coquelin wrote: When the slave cannot add queues dynamically, Could you please clarify the motivation a bit Why is it such a big deal to resize the queue array? We know no queues are used

Re: [Qemu-devel] [PATCH v4 08/14] i.MX: Add implementation of i.MX7 GPR IP block

On Mon, Jan 15, 2018 at 8:45 PM, Philippe Mathieu-Daudé wrote: > On 01/15/2018 10:37 PM, Andrey Smirnov wrote: >> Add minimal code needed to allow upstream Linux guest to boot. >> >> Cc: Peter Maydell >> Cc: Jason Wang >> Cc:

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: > > Correct me if I'm wrong, but it seems to me like there's no way > > to figure out through QMP whether these new machine options can be > > used for a given QEMU binary. > > Uh, I don't think so. These are machine options like any other

Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations

On 01/16/2018 03:59 AM, Peter Maydell wrote: > /var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: > internal compiler error: in emit_move_insn, at expr.c:3495 Bah. I remember seeing this myself on the gcc 4.8.x that is the system compiler on the gcc compile farm

Re: [Qemu-devel] [PATCH v4 13/14] hw/arm: Move virt's PSCI DT fixup code to arm/boot.c

On 16 January 2018 at 01:37, Andrey Smirnov wrote: > Move virt's PSCI DT fixup code to arm/boot.c and set this fixup to > happen automatically for every board that doesn't mark "psci-conduit" > as disabled. This way emulated boards other than "virt" that rely on > PSIC

[Qemu-devel] [PATCH v2 0/4] Implement Physical Presence interface for TPM 1.2 and 2

The following patches implement the TPM Physical Presence Interface that allows a user to set a command via ACPI (sysfs entry in Linux) that, upon the next reboot, the firmware (BIOS, UEFI) looks for an acts upon by sending sequences of commands to the TPM 1.2 or 2. My first goal is to get the

Re: [Qemu-devel] [PATCH v4 00/14] Initial i.MX7 support

On Tue, Jan 16, 2018 at 7:08 AM, Peter Maydell wrote: > On 16 January 2018 at 01:36, Andrey Smirnov wrote: >> Hi everyone, >> >> This v4 of the patch series containing the work that I've done in >> order to enable support for i.MX7 emulation in

Re: [Qemu-devel] [PATCH 05/11] virtio-ccw: convert VirtIOCCWDeviceClass::init -> realize

On 01/16/2018 09:07 AM, Philippe Mathieu-Daudé wrote: On 01/16/2018 10:41 AM, Farhan Ali wrote: shouldn't the commit message say exit -> unrealize? Oops, indeed :| Thanks :) Phil. Sure, you are welcome :) With the change in commit message, the patch looks good to me: Reviewed-by:

Re: [Qemu-devel] [PATCH x86-next v2] target-i386: add PCID flag to Westmere, Sandy Bridge and Ivy Bridge

On Tue, Jan 16, 2018 at 01:55:22PM +0100, Vincent Bernat wrote: > ❦ 16 janvier 2018 10:41 -0200, Eduardo Habkost  : > > >> > Adding Westmere-PCID would require adding a Westmere-PCID-IBRS > >> > CPU model too, so this is starting to look a bit ridiculous. > >> > Sane VM

Re: [Qemu-devel] [PATCH 0/3 v2] virtio: improve virtio devices initialization time

Hi Gal, Brilliant - will test this in the next day or two. Hopefully this will help resolve the issues I reported last summer. http://lists.nongnu.org/archive/html/qemu-devel/2017-07/msg05268.html Ray K On 14/01/2018 10:06, Gal Hammer wrote: A bug was reported about a very slow boot time and

Re: [Qemu-devel] [PATCH v2 2/3] xlnx-zynqmp-rtc: Add basic time support

On Mon, Jan 15, 2018 at 5:35 AM, Peter Maydell wrote: > On 12 January 2018 at 22:37, Alistair Francis > wrote: >> Allow the guest to determine the time set from the QEMU command line. >> >> This includes adding a trace event to debug the new

Re: [Qemu-devel] [PATCH v1] migration: use s->threshold_size inside migration_update_counters

On 01/16/2018 08:19 PM, Peter Xu wrote: On Tue, Jan 16, 2018 at 06:51:32PM +0800, Wei Wang wrote: The threshold size is changed to be recorded in s->threshold_size by commit b15df1ae5063c7c181f8f068f9eba7661b3b5e1. Signed-off-by: Wei Wang Could you help confirm the

[Qemu-devel] [PULL 13/22] spapr: Adjust default VSMT value for better migration compatibility

fa98fbfc "PC: KVM: Support machine option to set VSMT mode" introduced the "vsmt" parameter for the pseries machine type, which controls the spacing of the vcpu ids of thread 0 for each virtual core. This was done to bring some consistency and stability to how that was done, while still allowing

[Qemu-devel] [PULL 22/22] target-ppc: Fix booke206 tlbwe TLB instruction

From: Luc MICHEL When overwritting a valid TLB entry with a new one, the previous page were not flushed in QEMU TLB, leading to incoherent mapping. This commit fixes this. Signed-off-by: Luc MICHEL Signed-off-by: David Gibson

[Qemu-devel] [PULL 05/22] target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM

When constructing the "host" cpu class we modify whether the VMX and VSX vector extensions and DFP (Decimal Floating Point) are available based on whether KVM can support those instructions. This can depend on policy in the host kernel as well as on the actual host cpu capabilities. However, the

[Qemu-devel] [PULL 12/22] spapr: Allow some cases where we can't set VSMT mode in the kernel

At present if we require a vsmt mode that's not equal to the kernel's default, and the kernel doesn't let us change it (e.g. because it's an old kernel without support) then we always fail. But in fact we can cope with the kernel having a different vsmt as long as a) it's >= the actual number

[Qemu-devel] [PULL 19/22] ppc/pnv: fix XSCOM core addressing on POWER9

From: Cédric Le Goater The XSCOM base address of the core chiplet was wrongly calculated. Use the OPAL macros to fix that and do a couple of renames. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c

Re: [Qemu-devel] [PATCH 3/3] linux-user: MIPS set cpu to r6 CPU if binary is R6

On Sat, Jan 13, 2018 at 10:48 PM, Laurent Vivier wrote: > From: YunQiang Su > > So here we need to detect the version of binaries and set > cpu_model for it. > > [lv: original patch modified to move code into get_cpu_model()] > Signed-off-by: Laurent Vivier

Re: [Qemu-devel] [PULL 00/25] pc, pci, virtio: features, fixes, cleanups

On 2018年01月16日 16:03, Dmitry Fleytman wrote: On 16 Jan 2018, at 8:28, Jason Wang wrote: On 2018年01月16日 10:48, Michael S. Tsirkin wrote: On Tue, Jan 09, 2018 at 12:10:10PM +1100, David Gibson wrote: On Mon, Jan 08, 2018 at 08:10:23PM +0200, Michael S. Tsirkin wrote:

Re: [Qemu-devel] [PATCH] Add ability to provide ifname when using netdev bridge or tap helper

On 2018年01月17日 07:18, Shaun Reitan wrote: This patch replaces the patch I sent yesturday. This one fixes a bug in my original code as well as corrects a few styling issues. Hopfully this one comes out correct! Sorry for the inconvienece. When currently using -netdev bridge or -netdev tap

Re: [Qemu-devel] [PATCH v1] migration: use s->threshold_size inside migration_update_counters

On Wed, Jan 17, 2018 at 09:06:43AM +0800, Wei Wang wrote: > On 01/16/2018 08:19 PM, Peter Xu wrote: > > On Tue, Jan 16, 2018 at 06:51:32PM +0800, Wei Wang wrote: > > > The threshold size is changed to be recorded in s->threshold_size by > > > commit b15df1ae5063c7c181f8f068f9eba7661b3b5e1. > > >

Re: [Qemu-devel] [PATCH v2 4/4] linux-user: MIPS set cpu to r6 CPU if binary is R6

On 01/16/2018 02:25 PM, Laurent Vivier wrote: > From: YunQiang Su > > So here we need to detect the version of binaries and set > cpu_model for it. > > [lv: original patch modified to move code into cpu_get_model()] > Signed-off-by: Laurent Vivier > --- > >

Re: [Qemu-devel] [PATCH v2 03/32] qcow2: Remove BDS parameter from qcow2_cache_get_table_addr()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to get the > cache table size (since it was equal to the cluster size). This is no > longer necessary so this parameter can be removed. > > Signed-off-by: Alberto Garcia

Re: [Qemu-devel] [PATCH v2 04/32] qcow2: Remove BDS parameter from qcow2_cache_get_table_idx()

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > This function was only using the BlockDriverState parameter to get the > cache table size (since it was equal to the cluster size). This is no > longer necessary so this parameter can be removed. > > Signed-off-by: Alberto Garcia

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: > On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: > > > Correct me if I'm wrong, but it seems to me like there's no way > > > to figure out through QMP whether these new machine options can be > > > used for a given QEMU

Re: [Qemu-devel] [PATCH v2 20/32] qcow2: Update handle_copied() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > handle_copied() loads an L2 table and limits the number of checked > clusters to the amount that fits inside that table. Since we'll be > loading L2 slices instead of full tables we need to update that limit. > > Apart from that, this function

Re: [Qemu-devel] [PATCH v2 23/32] qcow2: Update zero_single_l2() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > zero_single_l2() limits the number of clusters to be zeroed to the > amount that fits inside an L2 table. Since we'll be loading L2 slices > instead of full tables we need to update that limit. > > Apart from that, this function doesn't need any

Re: [Qemu-devel] [PATCH v2 25/32] qcow2: Update expand_zero_clusters_in_l1() to support L2 slices

On 12/15/2017 06:53 AM, Alberto Garcia wrote: > expand_zero_clusters_in_l1() expands zero clusters as a necessary step > to downgrade qcow2 images to a version that doesn't support metadata > zero clusters. This function takes an L1 table (which may or may not > be active) and iterates over all

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Wed, Jan 17, 2018 at 10:26:28AM +1100, Alexey Kardashevskiy wrote: > On 17/01/18 09:34, David Gibson wrote: > > On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani wrote: > >> On Wed, 2018-01-17 at 00:54 +1100, David Gibson wrote: > Correct me if I'm wrong, but it seems to me like

[Qemu-devel] [PATCH v5 3/9] xlnx-zynqmp-pmu: Add the CPU and memory

Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- V4: - Remove the ZCU102 name V2: - Fix the pmu-cpu name - Use err and errp for CPU realise instead of

[Qemu-devel] [PATCH v5 4/9] aarch64-softmmu.mak: Use an ARM specific config

In preperation for having an ARM and MicroBlaze ZynqMP machine let's split out the current ARM specific config options. Signed-off-by: Alistair Francis Acked-by: Peter Maydell Reviewed-by: Edgar E. Iglesias ---

[Qemu-devel] [PATCH v5 6/9] xlnx-zynqmp-pmu: Connect the PMU interrupt controller

Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- hw/microblaze/xlnx-zynqmp-pmu.c | 24 1 file changed, 24 insertions(+) diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c

Re: [Qemu-devel] [PATCH v5 0/2] qemu-img: Document --force-share / -U

Ping? On Tue, Dec 26, 2017 at 10:52 AM, Fam Zheng wrote: > v5: Clean up the @table @var section first. [Kevin, Peter] > > Fam Zheng (2): > qemu-img.texi: Clean up parameter list > qemu-img: Document --force-share / -U > > qemu-img.texi | 75 >

Re: [Qemu-devel] [RFC v1] block/NVMe: introduce a new vhost NVMe host device to QEMU

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Wednesday, January 17, 2018 1:07 AM > To: Liu, Changpeng ; qemu-devel@nongnu.org > Cc: Harris, James R ; Busch, Keith > ;

[Qemu-devel] [PATCH v2] usb-storage: Fix share-rw option parsing

Because usb-storage creates an internal scsi device, we should propagate options. We already do so for bootindex etc, but failed to take care of share-rw. Fix it in an apparent way: add a new parameter to scsi_bus_legacy_add_drive and pass in s->conf.share_rw. Cc: qemu-sta...@nongnu.org

Re: [Qemu-devel] [PATCH] memory: update comments and fix some typos

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Tuesday, January 16, 2018 10:44 PM > To: Zhoujian (jay) ; qemu-devel@nongnu.org > Cc: Huangweidong (C) ; wangxin (U) > > Subject:

Re: [Qemu-devel] Qemu c++ build question

> On 17 Jan 2018, at 03:14, Ancuta, Cristian wrote: > > I'm currently working on implementing an emulation target in QEMU and the > implementation is in C++. it might not be the answer you expect, but last time I tried to do a similar thing I encountered a problem

Re: [Qemu-devel] [PATCH 4/7] docker: do not use Trusty APT source in Xenial

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: probably missed in 7fc581c29518 Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/dockerfiles/ubuntu.docker | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/docker/dockerfiles/ubuntu.docker

[Qemu-devel] [PULL 01/22] target/ppc: Yet another fix for KVM-HV HPTE accessors

From: Alexey Kardashevskiy As stated in the 1ad9f0a464fe commit log, the returned entries are not a whole PTEG. It was not a problem before 1ad9f0a464fe as it would read a single record assuming it contains a whole PTEG but now the code tries reading the entire PTEG and "if ((n -

[Qemu-devel] [PULL 07/22] spapr: Handle Decimal Floating Point (DFP) as an optional capability

Decimal Floating Point has been available on POWER7 and later (server) cpus. However, it can be disabled on the hypervisor, meaning that it's not available to guests. We currently handle this by conditionally advertising DFP support in the device tree depending on whether the guest CPU model

[Qemu-devel] [PULL 09/22] spapr: Remove unnecessary 'options' field from sPAPRCapabilityInfo

The options field here is intended to list the available values for the capability. It's not used yet, because the existing capabilities are boolean. We're going to add capabilities that aren't, but in that case the info on the possible values can be folded into the .description field.

[Qemu-devel] [PULL 06/22] spapr: Handle VMX/VSX presence as an spapr capability flag

We currently have some conditionals in the spapr device tree code to decide whether or not to advertise the availability of the VMX (aka Altivec) and VSX vector extensions to the guest, based on whether the guest cpu has those features. This can lead to confusion and subtle failures on migration,

[Qemu-devel] [PULL 03/22] spapr: Treat Hardware Transactional Memory (HTM) as an optional capability

This adds an spapr capability bit for Hardware Transactional Memory. It is enabled by default for pseries-2.11 and earlier machine types. with POWER8 or later CPUs (as it must be, since earlier qemu versions would implicitly allow it). However it is disabled by default for the latest

[Qemu-devel] [PULL 16/22] ppc/pnv: use POWER9 DD2 processor

From: Cédric Le Goater commit 1ed9c8af501f ("target/ppc: Add POWER9 DD2.0 model information") deprecated the POWER9 model v1.0. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 2 +-

Re: [Qemu-devel] [PATCH 0/7] docker: update Ubuntu and Fedora images, deprecate old ones

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: Hi, This series is to be clearer about which upstream version we are using. All "FROM distrib:latest" entries have now been removed and replaced by explicit "FROM distrib:version" ones. To keep backward compatibility, a warning is

Re: [Qemu-devel] [qemu-s390x] [PATCH v3 4/8] s390-ccw: interactive boot menu for eckd dasd (menu setup)

On 16.01.2018 20:37, Collin L. Walling wrote: > On 01/16/2018 01:23 PM, Thomas Huth wrote: >> On 15.01.2018 17:44, Collin L. Walling wrote: >>> Reads boot menu flag and timeout values from the iplb and >>> sets the respective fields for the menu. >>> >>> Signed-off-by: Collin L. Walling

Re: [Qemu-devel] Qemu c++ build question

Hi and thanks for the answer, Yes, not quite what I expected but your suggestion might indeed be the solution I need. Even if the problem that I'm encountering doesn't seeem to be related to the one you had, I'd will just export a C interface from the C++ code and keep the two isolated,

[Qemu-devel] [PULL 02/22] spapr: Capabilities infrastructure

Because PAPR is a paravirtual environment access to certain CPU (or other) facilities can be blocked by the hypervisor. PAPR provides ways to advertise in the device tree whether or not those features are available to the guest. In some places we automatically determine whether to make a feature

[Qemu-devel] [PULL 10/22] ppc: Change Power9 compat table to support at most 8 threads/core

From: Jose Ricardo Ziviani Increases the max smt mode to 8 for Power9. That's because KVM supports smt emulation in this platform so QEMU should allow users to use it as well. Today if we try to pass -smp ...,threads=8, QEMU will silently truncate it to smt4 mode and

[Qemu-devel] [PULL 00/22] ppc-for-2.12 queue 20180117

The following changes since commit 8e5dc9ba49743b46d955ec7dacb04e42ae7ada7c: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180116' into staging (2018-01-16 17:36:39 +) are available in the Git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.12-20180117

[Qemu-devel] [PULL 15/22] tests/boot-serial-test: fix powernv support

From: Cédric Le Goater Recent commit introduced the firmware image skiboot 5.9 which has a different first line ouput. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- tests/boot-serial-test.c | 2 +- 1 file changed, 1

Re: [Qemu-devel] [PATCH 0/3] target/ppc: add support for hypervisor doorbells

On Tue, Jan 16, 2018 at 08:41:54AM +0100, Cédric Le Goater wrote: > Hi, > > The hypervisor doorbells are used by skiboot and Linux on POWER9 > processors to wake up secondaries. This adds processor control support > to the Book3S architecture. > > The full tree can be found here : > >

Re: [Qemu-devel] [PATCH v2 0/4] Clean up the ppc configs

On Tue, Jan 16, 2018 at 01:15:54PM +0100, Thomas Huth wrote: > ppc64-softmmu is a superset of ppc-softmmu which in turn is a superset > of ppcemb-softmmu. But since the config files are currently independent > from each other, we missed to define some CONFIG switches in the super- > sets:

Re: [Qemu-devel] [PATCH v3 1/4] cryptodev: add vhost-user as a new cryptodev backend

> -Original Message- > From: Qemu-devel [mailto:qemu-devel- > bounces+jianjay.zhou=huawei@nongnu.org] On Behalf Of Michael S. Tsirkin > Sent: Wednesday, January 17, 2018 12:41 AM > To: Zhoujian (jay) > Cc: pa...@linux.vnet.ibm.com; Huangweidong (C)

Re: [Qemu-devel] [RFC 3/3] vhost-user: add VFIO based accelerators support

On Tue, Jan 16, 2018 at 10:23:39AM -0700, Alex Williamson wrote: > On Fri, 22 Dec 2017 14:41:51 +0800 > Tiwei Bie wrote: > > > Signed-off-by: Tiwei Bie > > --- > > docs/interop/vhost-user.txt| 57 ++ > > hw/vfio/common.c | 2 +-

[Qemu-devel] [PULL 18/22] ppc/pnv: introduce pnv*_is_power9() helpers

From: Cédric Le Goater These are useful when instantiating device models which are shared between the POWER8 and the POWER9 processor families. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_xscom.c | 8

Re: [Qemu-devel] [PATCH v4 13/13] docker: change Fedora images to run with python3

On 01/16/2018 01:02 AM, Daniel P. Berrange wrote: Fedora has switched to Python 3 by default, so it makes sense to use that for testing QEMU builds, so we get testing of Python 3 compatibility. Signed-off-by: Daniel P. Berrange ---

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 0/6] target/ppc: Rework spapr_caps

On Wed, Jan 17, 2018 at 10:46:45AM +1100, Alexey Kardashevskiy wrote: > On 17/01/18 10:30, David Gibson wrote: > > On Wed, Jan 17, 2018 at 10:26:28AM +1100, Alexey Kardashevskiy wrote: > >> On 17/01/18 09:34, David Gibson wrote: > >>> On Tue, Jan 16, 2018 at 03:46:20PM +0100, Andrea Bolognani

[Qemu-devel] Qemu c++ build question

I'm not sure this is the right way to ask this question - and I appollogize if it isn't - but here goes: I'm currently working on implementing an emulation target in QEMU and the implementation is in C++. I have the file qemu/target/mytarget/translate.cpp from which I #include and osdep.h

Re: [Qemu-devel] [PATCH 2/7] docker: do not display deprecated images in 'make docker' help

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: the 'debian' base image is deprecated since 3e11974988d8 Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/Makefile.include | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[Qemu-devel] [PULL 20/22] ppc/pnv: change initrd address

From: Cédric Le Goater When skiboot starts, it first clears the CPU structs for all possible CPUs on a system : for (i = 0; i <= cpu_max_pir; i++) memset(_stacks[i].cpu, 0, sizeof(struct cpu_thread)); On POWER9, cpu_max_pir is quite big, 0x7fff, and the

Re: [Qemu-devel] [PATCH v2 6/8] docker: add the Fedora 27 base image

On Tue, Jan 16, 2018 at 12:38 AM, Philippe Mathieu-Daudé wrote: > On 01/15/2018 01:27 PM, Daniel P. Berrange wrote: >> On Mon, Jan 15, 2018 at 11:34:57AM -0300, Philippe Mathieu-Daudé wrote: >>> straight copy on Fedora 25 base. >>> >>> Suggested-by: Paolo Bonzini

Re: [Qemu-devel] [PATCH 3/7] docker: add the Ubuntu Trusty base image

On 01/12/2018 08:49 PM, Philippe Mathieu-Daudé wrote: based on QEMU v2.10 ubuntu.docker (ca853f0c76e3 and 2346b12fc52d) Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/dockerfiles/ubuntu14.04.docker | 17 + 1 file changed, 17 insertions(+) create

[Qemu-devel] [PULL 04/22] spapr: Validate capabilities on migration

Now that the "pseries" machine type implements optional capabilities (well, one so far) there's the possibility of having different capabilities available at either end of a migration. Although arguably a user error, it would be nice to catch this situation and fail as gracefully as we can. This

[Qemu-devel] [PULL 11/22] target/ppc: Clarify compat mode max_threads value

We recently had some discussions that were sidetracked for a while, because nearly everyone misapprehended the purpose of the 'max_threads' field in the compatiblity modes table. It's all about guest expectations, not host expectations or support (that's handled elsewhere). In an attempt to

[Qemu-devel] [PULL 17/22] ppc/pnv: change core mask for POWER9

From: Cédric Le Goater When addressed by XSCOM, the first core has the 0x20 chiplet ID but the CPU PIR can start at 0x0. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv.c | 4 ++--

[Qemu-devel] [PULL 08/22] hw/ppc/spapr_caps: Rework spapr_caps to use uint8 internal representation

From: Suraj Jitindar Singh Currently spapr_caps are tied to boolean values (on or off). This patch reworks the caps so that they can have any uint8 value. This allows more capabilities with various values to be represented in the same way internally. Capabilities are

[Qemu-devel] [PULL 21/22] target/ppc: add support for POWER9 HILE

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- target/ppc/cpu.h | 1 + target/ppc/excp_helper.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h

Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations

gcc-4.8.5-16.el7_4.1.ppc64le On Tue, Jan 16, 2018 at 11:50 PM, Richard Henderson wrote: > On 01/16/2018 03:59 AM, Peter Maydell wrote: >> /var/tmp/patchew-tester-tmp-r7vd2rsz/src/accel/tcg/tcg-runtime-gvec.c:533:26: >> internal compiler error: in emit_move_insn, at

Re: [Qemu-devel] [PATCH 00/11] qdev: remove DeviceClass::init/exit()

Hi, This series failed docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180116131555.14242-1-f4...@amsat.org Subject: [Qemu-devel] [PATCH 00/11] qdev: remove

[Qemu-devel] [PATCH v1 1/4] virtio-balloon: VIRTIO_BALLOON_F_FREE_PAGE_VQ

The new feature enables the virtio-balloon device to receive the hint of guest free pages from the free page vq, and clears the corresponding bits of the free page from the dirty bitmap, so that those free pages are not transferred by the migration thread. Without this feature, to local live

Re: [Qemu-devel] [PATCH 3/3] linux-user: MIPS set cpu to r6 CPU if binary is R6

Le 17/01/2018 à 03:26, YunQiang Su a écrit : > On Sat, Jan 13, 2018 at 10:48 PM, Laurent Vivier wrote: >> From: YunQiang Su >> >> So here we need to detect the version of binaries and set >> cpu_model for it. >> >> [lv: original patch modified to move code

[Qemu-devel] [PATCH v1 2/4] migration: call balloon to clear bits of free pages from dirty bitmap

When migration starts, call the related balloon functions to clear the bits of guest free pages from the dirty bitmap. The dirty bitmap should be ready to use when sending pages to the destination, so stop the guest from reporting free pages before sending pages. Signed-off-by: Wei Wang

[Qemu-devel] [PATCH v1 3/4] virtio-balloon: add a timer to limit the free page report wating time

This patch adds a timer to limit the time that the host waits for the free pages reported by the guest. Users can specify the time in ms via "free-page-wait-time" command line option. If a user doesn't specify a time, the host waits till the guest finishes reporting all the free pages. The policy

[Qemu-devel] [PATCH v1 4/4] virtio-balloon: Don't skip free pages if the poison val is non-zero

If the guest is using a non-zero poisoning, we don't skip the transfer of guest free pages. Todo: As a next step optimization, we can try 1) skip the transfer of guest poisoned free pages; 2) send the poison value to destination; and 3) seek a way to poison the guest free pages before the guest

[Qemu-devel] [PATCH v1 0/4] virtio-balloon: support free page reporting

This is the deivce part implementation to add a new feature, VIRTIO_BALLOON_F_FREE_PAGE_VQ to the virtio-balloon device. The device receives the guest free page hint from the driver and clears the corresponding bits in the dirty bitmap, so that those free pages are not transferred to the

Re: [Qemu-devel] [RFC v1] block/NVMe: introduce a new vhost NVMe host device to QEMU

On 17/01/2018 01:53, Liu, Changpeng wrote: >> Second, virtio-based vhost-user remains QEMU's preferred method for >> high-performance I/O in guests. Discard support is missing and that is >> important for SSDs; that should be fixed in the virtio spec. Are there > Previously I have a patch adding

Re: [Qemu-devel] [PATCH v2 0/4] coroutine-lock: polymorphic CoQueue

On 01/17/2018 02:04 PM, no-re...@patchew.org wrote: BUILD min-glib Traceback (most recent call last): File "./tests/docker/docker.py", line 407, in sys.exit(main()) File "./tests/docker/docker.py", line 404, in main return args.cmdobj.run(args, argv) File

Re: [Qemu-devel] [PATCH v2 0/4] coroutine-lock: polymorphic CoQueue

Hi, This series failed docker-build@min-glib build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180116142316.30486-1-pbonz...@redhat.com Subject: [Qemu-devel] [PATCH v2 0/4]

[Qemu-devel] [PATCH v2 1/4] default-configs/ppc64-softmmu: Include 32-bit configs instead of copying them

qemu-softmmu-ppc64 is supposed to be a superset of qemu-softmmu-ppc. However, instead of simply including the 32-bit config file, we've duplicated all CONFIG_xxx settings there instead. This way, we've missed some CONFIG switches in ppc64-softmmu.mak which were only added to the 32-bit config file

Re: [Qemu-devel] [PATCH x86-next v2] target-i386: add PCID flag to Westmere, Sandy Bridge and Ivy Bridge

On Sat, Jan 13, 2018 at 08:22:31AM +0100, Vincent Bernat wrote: > ❦ 12 janvier 2018 16:47 -0200, Eduardo Habkost  : > > > Adding Westmere-PCID would require adding a Westmere-PCID-IBRS > > CPU model too, so this is starting to look a bit ridiculous. > > Sane VM management

Re: [Qemu-devel] [PULL 00/33] pc, pci, virtio: features, fixes, cleanups

* Peter Maydell (peter.mayd...@linaro.org) wrote: > On 16 January 2018 at 04:46, Michael S. Tsirkin wrote: > > A large pull due to patch buildup over the holiday period. > > Most notable here is probably the addition of vhost-user-blk. > > > > The following changes since commit

[Qemu-devel] [PATCH v6 1/9] mirror: inherit supported write/zero flags

Signed-off-by: Anton Nefedov Reviewed-by: Eric Blake Reviewed-by: Alberto Garcia --- block/mirror.c | 5 + 1 file changed, 5 insertions(+) diff --git a/block/mirror.c b/block/mirror.c index c9badc1..d18ec65 100644 ---

[Qemu-devel] [PATCH 07/11] qdev: simplify the SysBusDeviceClass::init path

The SysBusDevice is the last DeviceClass::init user. Instead of using SysBusDeviceClass::realize -> DeviceClass::realize -> DeviceClass::init -> sysbus_device_init -> SysBusDeviceClass::init Simplify the path by directly calling SysBusDeviceClass::init in

Re: [Qemu-devel] [PATCH 5/5] tests: acpi: fix FADT not being compared to reference table

On Tue, 16 Jan 2018 06:16:34 +0200 "Michael S. Tsirkin" wrote: > On Fri, Dec 29, 2017 at 04:16:42PM +0100, Igor Mammedov wrote: > > It turns out that FADT isn't actually tested for changes > > against reference table, since it happens to be the 1st > > table in RSDT which is

[Qemu-devel] [PATCH 03/11] hw/i2c: convert I2CSlaveClass::init -> realize

Signed-off-by: Philippe Mathieu-Daudé --- include/hw/i2c/i2c.h| 2 +- include/hw/i2c/smbus.h | 2 +- hw/audio/wm8750.c | 8 +++- hw/display/ssd0303.c| 5 ++--- hw/gpio/max7310.c | 6 ++ hw/i2c/core.c | 10 -- hw/i2c/smbus.c

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