Since f3218a8 ("softfloat: add floatx80 constants")
floatx80_infinity is defined but never used.
This patch updates floatx80 functions to use
this definition.
This allows to define a different default Infinity
value on m68k: the m68k FPU defines infinity with
all bits set to zero in the mantissa.
Using local m68k floatx80_getman(), floatx80_getexp(), floatx80_scale()
[copied from previous:
Written by Andreas Grabher for Previous, NeXT Computer Emulator.]
Signed-off-by: Laurent Vivier
---
target/m68k/fpu_helper.c | 15 +
target/m68k/helper.h | 3 +
target/m68k/softfloat.c | 14
When using qemu pcie_aer_inject_error command to inject
an error on e1000e, the error is not sent to the guest.
The problem is caused by the e1000e did not initialize
the device error control registers mask. Since the
default mask is 0, any value written to the registers
will be masked off.
Follow
On 02/23/2018 03:57 PM, Collin L. Walling wrote:
> On 02/23/2018 05:11 AM, Christian Borntraeger wrote:
>>
>> On 02/23/2018 11:07 AM, Thomas Huth wrote:
>>> On 22.02.2018 20:40, Collin L. Walling wrote:
On 02/22/2018 11:45 AM, Collin L. Walling wrote:
> On 02/22/2018 10:44 AM, Christian
On 02/23/2018 08:33 AM, Thomas Huth wrote:
On 23.02.2018 12:50, Viktor Mihajlovski wrote:
On 23.02.2018 11:17, Thomas Huth wrote:
On 23.02.2018 09:53, Christian Borntraeger wrote:
Hmmm, on my ubuntu 16.04 guest, I get the boot menu with no timeout even if I
do not
specify loadparm or boot men
On 02/21/2018 07:53 AM, Kevin Wolf wrote:
This adds the .bdrv_co_create driver callback to gluster, which enables
image creation over QMP.
Signed-off-by: Kevin Wolf
---
qapi/block-core.json | 18 ++-
block/gluster.c | 135 ++-
2 file
On Fri, 23 Feb 2018 15:27:02 +0100
Christian Borntraeger wrote:
[...]
> > +/* copy up to dst_len bytes and fill the rest of dst with zeroes
> > */
>
> you just moved this function but shouldnt it be
>
> src_len bytes and fill will zeroes until dst_len?
true, will fix
[...]
On 02/21/2018 07:53 AM, Kevin Wolf wrote:
If we want to include the invalid option name in the error message, we
can't free the string earlier than that.
Signed-off-by: Kevin Wolf
---
block/rbd.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
D'oh. Should this one be cc'd to qemu
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 6 +
> target/arm/sve_helper.c| 280
> +
> target/arm/translate-sve.c | 110 ++
> target/arm/sve.decod
Am 23.02.2018 um 00:10 hat Max Reitz geschrieben:
> On 2018-02-21 14:53, Kevin Wolf wrote:
> > The code to establish an RBD connection is duplicated between open and
> > create. In order to be able to share the code, factor out the code from
> > qemu_rbd_open() as a first step.
> >
> > Signed-off-
On 02/21/2018 07:54 AM, Kevin Wolf wrote:
If bdrv_truncate() is called, but the requested size is the same as
before, don't call posix_fallocate(), which returns -EINVAL for length
zero and would therefore make bdrv_truncate() fail.
The problem can be triggered by creating a zero-sized raw image
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 15 ++
> target/arm/sve_helper.c| 72
> ++
> target/arm/translate-sve.c | 69 +++
Am 21.02.2018 um 14:53 hat Kevin Wolf geschrieben:
> The "redundacy" option for Sheepdog image creation is currently a string
> that can encode one or two integers depending on its format, which at
> the same time implicitly selects a mode.
>
> This patch turns it into a QAPI union and converts th
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 3 +++
> target/arm/sve_helper.c| 34 ++
> target/arm/translate-sve.c | 12
> target/arm/sve.decode | 6 ++
>
There is code checking s->end_transfer_func and it was not taught
about ide_transfer_cancel. We can just use ide_transfer_stop because
s->end_transfer_func is only ever called in the DRQ phase: after
ide_transfer_cancel, the value of s->end_transfer_func is only used
as a marker and never used to
The callback must be invoked once we get out of the DRQ phase; because
all end_transfer_funcs end up invoking ide_transfer_stop, call it there.
While at it, remove the "notify" argument from ide_transfer_halt; the
code can simply be moved to ide_transfer_stop.
Old PATA controllers have no end_tran
Split the PIO transfer across two callbacks, thus pushing the (possibly
recursive) call to end_transfer_func up one level and out of the
AHCI-specific code.
Signed-off-by: Paolo Bonzini
---
hw/ide/ahci.c | 7 ++-
hw/ide/core.c | 9 ++---
include/hw/ide/internal.h
The ATAPI_INT_REASON_IO interrupt is raised when I/O starts, but in the
AHCI case ide_set_irq was actually called at the end of a mutual recursion.
Move it early, with the side effect that ide_transfer_start becomes a tail
call in ide_atapi_cmd_reply_end.
Signed-off-by: Paolo Bonzini
---
hw/ide/
Real hardware doesn't have an unlimited stack, so the unlimited
recursion in the ATAPI code smells a bit. In fact, the call to
ide_transfer_start easily becomes a tail call with a small change
to the code (patch 4). The remaining four patches move code around
so as to the turn the call back to id
For the case where the end_transfer_func is also the caller of
ide_transfer_start, the mutual recursion can lead to unlimited
stack usage. Introduce a new version that can be used to change
tail recursion into a loop, and use it in trace_ide_atapi_cmd_reply_end.
Signed-off-by: Paolo Bonzini
---
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 267a9d7e2f..c2bce23fa5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -168,6 +168,7 @@ typedef struct {
* Qn =
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/exec/helper-head.h | 3 +++
1 file changed, 3 in
We do implement all the opcodes.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/translate-a64.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ebaf4571ac..5dd54b7ac4 100644
--- a/targe
Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.
Signed-off-by: Alex Bennée
--
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8c839faa8f..267a9d7e2f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1408,6 +1408,
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
--
v1
- dropped the
Now that the softfloat re-factoring has been merged I re-based this
directly from master. Alternatively you can grab the full tree from:
https://github.com/stsquad/qemu/tree/arm-fp16-v3
I've tested with the following RISU test binaries:
http://people.linaro.org/~alex.bennee/testcases/arm64.
This covers the encoding group:
Advanced SIMD scalar three same FP16
As all the helpers are already there it is simply a case of calling the
existing helpers in the scalar context.
Signed-off-by: Alex Bennée
---
v2
- checkpatch fixes
v3
- check for FP16 feature
- remove stray debug
-
This is the initial decode skeleton for the Advanced SIMD three same
instruction group.
The fprintf is purely to aid debugging as the additional instructions
are added. It will be removed once the group is complete.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/trans
As the rounding mode is now split between FP16 and the rest of
floating point we need to be explicit when tweaking it. Instead of
passing the CPU env we now pass the appropriate fpst pointer directly.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/helper.c| 4
These use the generic float16_compare functionality which in turn uses
the common float_compare code from the softfloat re-factor.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/helper-a64.c| 49 ++
target/arm/helper-a64.
This covers all the floating point convert operations.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/helper-a64.c| 32 +
target/arm/helper-a64.h| 2 ++
target/arm/translate-a64.c | 85 +-
3 files cha
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/helper-a64.c| 24
target/arm/helper-a64.h| 2 ++
target/arm/translate-a64.c | 15 +++
3 files changed, 41 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper
The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
v2
- add absh helper
- fix checkpatch violation
- make abs a bitwise operation
---
target/arm/helper-a64.c|
I've re-factored the handle_simd_intfp_conv helper to properly handle
half-precision as well as call plain conversion helpers when we are
not doing fixed point conversion.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/helper.c| 4 ++
target/arm/helper.h
I only needed to do a little light re-factoring to support the
half-precision helpers.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/translate-a64.c | 80 +++---
1 file changed, 54 insertions(+), 26 deletions(-)
diff --git a/ta
This adds the full range of half-precision floating point to integral
instructions.
Signed-off-by: Alex Bennée
---
v3
- fix re-base conflicts
- move comment to previous commit
- don't double test is_scalar in unallocated checks
---
target/arm/helper-a64.c| 22
target/arm/hel
This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.
Signed-off-by: Alex Bennée
---
v2
- checkpatch fixes
---
target/arm/translate-a64.c | 208 +
1 file changed, 133 insertions(+), 75 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/ar
A bunch of the vectorised bitwise operations just operate on larger
chunks at a time. We can do the same for the new half-precision
operations by introducing some TWOHALFOP helpers which work on each
half of a pair of half-precision operations at once.
Hopefully all this hoop jumping will get simp
This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use
existing helpers to achieve this.
Signed-off-by: Alex Bennée
---
v3
- make fabs a bitwise operation
- use read_vec_element_i32 to read value
- properly wire into disas_fp_1rc
---
target/arm/translate-a64.c | 71 +
This actually covers two different sections of the encoding table:
Advanced SIMD scalar two-register miscellaneous FP16
Advanced SIMD two-register miscellaneous (FP16)
The difference between the two is covered by a combination of Q (bit
30) and S (bit 28). Notably the FRINTx instructions ar
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/translate-a64.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ba3926262e..faec8084fa 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/transl
Much like recpe the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final
Add new cylinder/head/sector struct. Use it to calculate
eckd block numbers instead of a BootMapPointer (which used
eckd chs anyway).
Signed-off-by: Collin L. Walling
Reviewed-by: Thomas Huth
---
pc-bios/s390-ccw/bootmap.c | 28 ++--
pc-bios/s390-ccw/bootmap.h | 8 +
Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).
Signed-off-by: Alex Bennée
---
v3
- fixup re-base conflicts
- make both operations pure bitwise TCG
---
target/arm/translat
ECKD DASDs have different IPL structures for CDL and LDL
formats. The current Ipl1 and Ipl2 structs follow the CDL
format, so we prepend "EckdCdl" to them. Boot info for LDL
has been moved to a new struct: EckdLdlIpl1.
Signed-off-by: Collin L. Walling
Acked-by: Janosch Frank
Reviewed-by: Thomas
The helpers use the new re-factored muladd support in SoftFloat for
the float16 work.
Signed-off-by: Alex Bennée
---
v3
- re-jigged switch statement to fall-through for unalloc
- added is_fp16 bool for fpst
- fixed up some long lines
---
target/arm/translate-a64.c | 83 +++
Moved:
memcmp from bootmap.h to libc.h (renamed from _memcmp)
strlen from sclp.c to libc.h (renamed from _strlen)
Added C standard functions:
isdigit
Added non C-standard function:
uitoa
atoui
Signed-off-by: Collin L. Walling
Acked-by: Christian Borntraeger
Reviewed-by: Janosch Frank
Only one half-precision instruction has been added to this group.
Signed-off-by: Alex Bennée
---
v2
- checkpatch fixes
v3
- use vfp_expand_imm
---
target/arm/translate-a64.c | 35 +--
1 file changed, 25 insertions(+), 10 deletions(-)
diff --git a/target/arm/
--- [v9] ---
- only set boot menu opts if a bootindex was specified on cmd
- Menus for guests with an IPL device that chooses to use the SCSI scheme are
only enabled explicitly for -boot menu=on options (i.e. it will appropriately
and cleanly ignore the zipl flag)
--- [Summary] ---
Thes
The s390-ccw firmware needs some information in support of the
boot process which is not available on the native machine.
Examples are the netboot firmware load address and now the
boot menu parameters.
While storing that data in unused fields of the IPL parameter block
works, that approach could
Read the stage2 boot loader data block-by-block. We scan the
current block for the string "zIPL" to detect the start of the
boot menu banner. We then load the adjacent blocks (previous
block and next block) to account for the possibility of menu
data spanning multiple blocks.
Signed-off-by: Collin
We go with the localised helper.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/helper-a64.c| 29 +
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.c | 4
3 files changed, 34 insertions(+)
diff --git a/target/arm/helpe
Some ECKD bootmap code was using structs designed for SCSI.
Even though this works, it confuses readability. Add a new
BootMapTable struct to assist with readability in bootmap
entry code. Also:
- replace ScsiMbr in ECKD code with appropriate structs
- fix read_block messages to reflect BootMapTab
It is possible while waiting for multiple types of external
interrupts that we might have pending irqs remaining between
irq consumption and irq-type disabling. Those interrupts
could potentially propagate to the guest after IPL completes
and cause unwanted behavior.
As it is today, the SCLP will
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 2 +
> target/arm/sve_helper.c| 11 ++
> target/arm/translate-sve.c | 299
> +
> target/arm/sve.decode | 20 +++
It looks like the ARM ARM has simplified the pseudo code for the
calculation which is done on a fixed point 9 bit integer maths. So
while adding f16 we can also clean this up to be a little less heavy
on the floating point and just return the fractional part and leave
the calle's to do the final pa
Set boot menu options for an s390 guest and store them in
the iplb. These options are set via the QEMU command line
option:
-boot menu=on|off[,splash-time=X]
or via the libvirt domain xml:
Where X represents some positive integer representing
milliseconds.
Any value set fo
Implements an sclp_read function to capture input from the
console and a wrapper function that handles parsing certain
characters and adding input to a buffer. The input is checked
for any erroneous values and is handled appropriately.
A prompt will persist until input is entered or the timeout
ex
Hi,
This is essentially a re-post but with a wider distribution. There is
one extra patch which adds the FP16 1 source data processing. This is for
discussion on how best to represent all the different architectural
versions by using the second field in the aarch64.risu file.
Alex Bennée (8):
r
Now we have added f16 during the re-factoring we can simply call the
helper.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
target/arm/translate-a64.c | 8
1 file changed, 8 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 00b04d3
Reads boot menu flag and timeout values from the iplb and
sets the respective fields for the menu.
Signed-off-by: Collin L. Walling
Reviewed-by: Thomas Huth
---
pc-bios/s390-ccw/Makefile | 2 +-
pc-bios/s390-ccw/main.c | 24
pc-bios/s390-ccw/menu.c | 22 +
Interactive boot menu for scsi. This follows a similar procedure
as the interactive menu for eckd dasd. An example follows:
s390x Enumerated Boot Menu.
3 entries detected. Select from index 0 to 2.
Signed-off-by: Collin L. Walling
Reviewed-by: Thomas Huth
---
hw/s390x/ipl.c
The existing pattern support is useful but it does get a little
tedious when faced with large groups of instructions. This introduces
the concept of a @GroupName which can be sprinkled in the risu
definition and is attached to all instructions following its
definition until the next group or an emp
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.
Signed-off-by: Alex Bennée
---
v3
- use size directly wuth read/write_vec_element
- drop unneeded break
- WIP: mess with calculating maxpasses
---
target/arm/translate-a64.c |
If no boot menu options are present, then flag the boot menu to
use the zipl options that were set in the zipl configuration file
(and stored on disk by zipl). These options are found at some
offset prior to the start of the zipl boot menu banner. The zipl
timeout value is limited to a 16-bit unsig
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate-sve.c | 13 +
> target/arm/sve.decode | 6 ++
> 2 files changed, 19 insertions(+)
>
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
This is a simple script for generating all instructions in a given
RISU file. You can split up the batch size by passing a -n N command
line options. For example:
./contrib/generate_all.sh -n 2 hp.risu testcases.armv8.2_hp
Signed-off-by: Alex Bennée
---
contrib/generate_all.sh | 96 ++
When the boot menu options are present and the guest's
disk has been configured by the zipl tool, then the user
will be presented with an interactive boot menu with
labeled entries. An example of what the menu might look
like:
zIPL v1.37.1-build-20170714 interactive boot menu.
0. default (linux-4
Signed-off-by: Alex Bennée
---
aarch64.risu | 32
1 file changed, 32 insertions(+)
diff --git a/aarch64.risu b/aarch64.risu
index 838bded..06a9f3c 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2937,3 +2937,35 @@ FCVTZUsi_RES A64_V sf:1 000 1 type:1 1 11 00
This adds the half-precision encoding and shuffles around the RES
space to indicate this.
Signed-off-by: Alex Bennée
---
aarch64.risu | 55 +++
1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/aarch64.risu b/aarch64.risu
index 06
On 02/23/18 14:23, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Hi,
>
> The following series adds basic TPM2 support for OVMF-on-QEMU (I
> haven't tested TPM1, for lack of interest). It links with the modules
> to initializes the device in PEI phase, and do measurements (both
Useful if you want to disable a feature for your run. For example:
set -x QEMU_FLAGS "-cpu fp16=off"
Signed-off-by: Alex Bennée
---
contrib/run_risu.sh | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/contrib/run_risu.sh b/contrib/run_risu.sh
index 439cd36..63649dd 10
It saves you from having to check the status code or wonder if the
errors just scrolled off your screen.
Signed-off-by: Alex Bennée
---
contrib/run_risu.sh | 2 ++
1 file changed, 2 insertions(+)
diff --git a/contrib/run_risu.sh b/contrib/run_risu.sh
index 2d1897a..fc69d83 100755
--- a/contrib/
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
v2
remove superfluous helpers
---
target/arm/helper-a64.c| 13 +
target/arm/helper-a64.h| 1 +
target/arm/translate-a64.c | 5 +
3 files changed, 19 insertions(+)
diff --git a/target/arm/helper-a64.c b/tar
As the script is meant to summarise the results at the end it doesn't
make sense to bail out at the first error.
Signed-off-by: Alex Bennée
---
contrib/run_risu.sh | 2 --
1 file changed, 2 deletions(-)
diff --git a/contrib/run_risu.sh b/contrib/run_risu.sh
index 63649dd..2d1897a 100755
--- a/c
On 23.02.2018 16:43, Collin L. Walling wrote:
> Interactive boot menu for scsi. This follows a similar procedure
> as the interactive menu for eckd dasd. An example follows:
>
> s390x Enumerated Boot Menu.
>
> 3 entries detected. Select from index 0 to 2.
>
> Signed-off-by: Collin L. Wal
Am 23.02.2018 um 16:15 hat Eric Blake geschrieben:
> On 02/21/2018 07:53 AM, Kevin Wolf wrote:
> > If we want to include the invalid option name in the error message, we
> > can't free the string earlier than that.
> >
> > Signed-off-by: Kevin Wolf
> > ---
> > block/rbd.c | 3 ++-
> > 1 file c
On 02/23/18 14:23, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Apparently, unnecessary. Avoids extra build dependency and churn.
>
> CC: Laszlo Ersek
> CC: Stefan Berger
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Marc-André Lureau
> ---
>
Clean-up the risu definitions by:
- removing out-dated section numbers
- fixing section titles to match ASL encoding groups
- add @Section markers
Signed-off-by: Alex Bennée
---
aarch64.risu | 200 +--
1 file changed, 141 insertions(+
As some of the constants here will also be needed
elsewhere (specifically for the upcoming SVE support) we move them out
to softfloat.h.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
v3
- move constants used for estimate to softfloat.h
---
include/fpu/softfloat.h| 16
This unifies 5 copies of checks for supported vector size,
and in the process fixes a missing check in tcg_gen_gvec_2s.
This lead to an assertion failure for 64-bit vector multiply,
which is not available in the AVX instruction set.
Suggested-by: Peter Maydell
Signed-off-by: Richard Henderson
-
On Fri, 23 Feb 2018 09:53:22 +0100
Gerd Hoffmann wrote:
> Hi,
>
> > > What type of device is only sometimes hotpluggable ?
> > > The commit message says "display devices" and "consoles",
> > > but I would expect those to both be types of device which
> > > have a class which is never hotplugga
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 2 ++
> target/arm/sve_helper.c| 37 +
> target/arm/translate-sve.c | 10 ++
> target/arm/sve.decode | 3 +++
> 4
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 14 ++
> target/arm/sve_helper.c| 41 ++---
> target/arm/translate-sve.c | 38 ++
On 02/23/2018 11:03 AM, Thomas Huth wrote:
On 23.02.2018 16:43, Collin L. Walling wrote:
The s390-ccw firmware needs some information in support of the
boot process which is not available on the native machine.
Examples are the netboot firmware load address and now the
boot menu parameters.
Whi
On 23.02.2018 16:43, Collin L. Walling wrote:
> --- [v9] ---
>
> - only set boot menu opts if a bootindex was specified on cmd
>
> - Menus for guests with an IPL device that chooses to use the SCSI scheme are
>only enabled explicitly for -boot menu=on options (i.e. it will
> appropriately
On 30 January 2018 at 16:25, Peter Maydell wrote:
> It seems like it's about time we settled on the dates for the
> 2.12 release. I've sketched in a suggestion at:
> https://wiki.qemu.org/Planning/2.12
>
> which puts softfreeze on the 13th March, hardfreeze a
> week later on the 20th, and final
On 23.02.2018 16:43, Collin L. Walling wrote:
> The s390-ccw firmware needs some information in support of the
> boot process which is not available on the native machine.
> Examples are the netboot firmware load address and now the
> boot menu parameters.
>
> While storing that data in unused fie
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 9
> target/arm/sve_helper.c| 55
> ++
> target/arm/translate-sve.c | 2 ++
> target/arm/sve.decode | 6
On Fri, Feb 23, 2018 at 03:46:09PM +, Alex Bennée wrote:
> This is a simple script for generating all instructions in a given
> RISU file. You can split up the batch size by passing a -n N command
> line options. For example:
>
> ./contrib/generate_all.sh -n 2 hp.risu testcases.armv8.2_hp
>
Am 23.02.2018 um 00:25 hat Max Reitz geschrieben:
> On 2018-02-21 14:53, Kevin Wolf wrote:
> > With the conversion to a QAPI options object, the function is now
> > prepared to be used in a .bdrv_co_create implementation.
> >
> > Signed-off-by: Kevin Wolf
> > -*s_snap = g_strdup(snap);
> > -
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
> index 86cd792cdf..ae433861f8 100644
> --- a/target/arm/sve_helper.c
> +++ b/target/arm/sve_helper.c
> @@ -46,14 +46,14 @@
> *
> *
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 44 +++
> target/arm/sve_helper.c| 88
> ++
> target/arm/translate-sve.c | 63 ++
On Tue, Feb 13, 2018 at 02:00:29PM +, Peter Maydell wrote:
> A persistent build problem we see is where a source file
> accidentally omits the #include of log.h. This slips through
> local developer testing because if you configure with the
> default (log) trace backend trace.h will pull in log
On 17 February 2018 at 18:22, Richard Henderson
wrote:
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper-sve.h| 18
> target/arm/sve_helper.c| 247
> +
> target/arm/translate-sve.c | 96 ++
> target/arm/sve.de
On 02/14/2018 06:05 AM, Kevin Wolf wrote:
+static int coroutine_fn null_co_block_status(BlockDriverState *bs,
if (s->read_zeroes) {
-return BDRV_BLOCK_OFFSET_VALID | start | BDRV_BLOCK_ZERO;
-} else {
-return BDRV_BLOCK_OFFSET_VALID | start;
+ret |= BDRV_BLOC
On 23 February 2018 at 16:17, Daniel P. Berrangé wrote:
> On Fri, Feb 23, 2018 at 03:46:09PM +, Alex Bennée wrote:
>> This is a simple script for generating all instructions in a given
>> RISU file. You can split up the batch size by passing a -n N command
>> line options. For example:
>>
>>
On 2018-02-23 17:19, Kevin Wolf wrote:
> Am 23.02.2018 um 00:25 hat Max Reitz geschrieben:
>> On 2018-02-21 14:53, Kevin Wolf wrote:
>>> With the conversion to a QAPI options object, the function is now
>>> prepared to be used in a .bdrv_co_create implementation.
>>>
>>> Signed-off-by: Kevin Wolf
Daniel P. Berrangé writes:
> On Fri, Feb 23, 2018 at 03:46:09PM +, Alex Bennée wrote:
>> This is a simple script for generating all instructions in a given
>> RISU file. You can split up the batch size by passing a -n N command
>> line options. For example:
>>
>> ./contrib/generate_all.sh
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