From: Weiwei Li
The spec for vmvr.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Message-Id:
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Richard Henderson
Message-Id: <20220317061817.3856850-2-alistair.fran...@opensource.wdc.com>
---
target/riscv/cpu.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --gi
From: Atish Patra
Virt machine uses privileged specification version 1.12 now.
All other machine continue to use the default one defined for that
machine unless changed to 1.12 by the user explicitly.
This commit enforces the privilege version for csrs introduced in
v1.12 or after.
Reviewed-by:
From: Frank Chang
If device's MemoryRegion doesn't have .impl.[min|max]_access_size
declaration, the default access_size_min would be 1 byte and
access_size_max would be 4 bytes (see: softmmu/memory.c).
This will cause a 64-bit memory access to ACLINT to be splitted into
two 32-bit memory accesse
From: Nicolas Pitre
There is an overflow with the current code where a pmpaddr value of
0x1fff is decoded as sa=0 and ea=0 whereas it should be sa=0 and
ea=0x.
Fix that by simplifying the computation. There is in fact no need for
ctz64() nor special case for -1 to achieve proper resu
From: Weiwei Li
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share
the same helper
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-Id: <20220325085902.29500-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Fra
From: Tsukasa OI
Some bits in RISC-V `misa' CSR should not be reflected in the ISA
string. For instance, `S' and `U' (represents existence of supervisor
and user mode, respectively) in `misa' CSR must not be copied since
neither `S' nor `U' are valid single-letter extensions.
This commit also r
From: Bin Meng
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-4-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4
From: Frank Chang
RISC-V privilege spec defines that mtime is exposed as a memory-mapped
machine-mode read-write register. However, as QEMU uses host monotonic
timer as timer source, this makes mtime to be read-only in RISC-V
ACLINT.
This patch makes mtime to be writable by recording the time de
From: Bin Meng
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 tri
From: Richard Henderson
The riscv_raise_exception function stores its argument into
exception_index and then exits to the main loop. When we
have already set exception_index, we can just exit directly.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220401125948.
From: Dylan Jhong
The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram
address within 3GB,
but not all platforms have dram_base within 3GB.
This patch adds an exception for dram base not within 3GB,
which will place fdt at dram_end align 16MB.
riscv_setup_rom_reset_vec() al
On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote:
>
> On Wed, Apr 20, 2022 at 5:57 PM wrote:
> >
> > From: Frank Chang
> >
> > Allow user to set core's marchid, mvendorid, mipid CSRs through
> > -cpu command line option.
> >
> > The default values of marchid and mipid are built with QEMU's versio
From: Ralf Ramsauer
The -bios option is silently ignored if used in combination with -enable-kvm.
The reason is that the machine starts in S-Mode, and the bios typically runs in
M-Mode.
Better exit in that case to not confuse the user.
Signed-off-by: Ralf Ramsauer
Reviewed-by: Alistair Francis
On 3/10/2022 9:07 PM, Michael S. Tsirkin wrote:
On Thu, Mar 10, 2022 at 08:28:09PM +0800, Xiaoyao Li wrote:
For PIT, it's straightforward to merge microvm::pit and
pc_machine::pit_enabled into x86ms::pit
For PIC, move microvm::pic to x86ms:pic, which gives PC machine the
ability to dis-/en-able
From: Bin Meng
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-3-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
From: Niklas Cassel
The device tree property "mmu-type" is currently exported as either
"riscv,sv32" or "riscv,sv48".
However, the riscv cpu device tree binding [1] has a specific value
"riscv,none" for a HART without a MMU.
Set the device tree property "mmu-type" to "riscv,none" when the CPU m
On Thu, Apr 21, 2022 at 3:57 PM Bin Meng wrote:
>
> From: Bin Meng
>
> At present the adding '/chosen/stdout-path' property in device tree
> is determined by whether a kernel command line is provided, which is
> wrong. It should be added unconditionally.
>
> Fixes: 8d8897accb1c ("hw/riscv: spike:
From: Frank Chang
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to
From: Jim Shu
This commit implements reset function of all ACLINT devices.
ACLINT device reset will clear MTIME and MSIP register to 0.
Depend on RISC-V ACLINT spec v1.0-rc4:
https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
On Thu, Apr 21, 2022 at 3:58 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
> tried to avoid adding *NULL* bootargs to device tree, but unfortunately
> the changes were entirely useless, due to MachineState::kernel_cmdline
> can't
From: Bin Meng
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-2-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/deb
From: Bin Meng
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-5-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/machine.c | 32
1 file ch
From: Bin Meng
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-7-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
include/hw/core/tcg-cpu-ops.h | 1 +
1 f
From: Bin Meng
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-Id: <20220421003324.1134983-6-bmeng...@gmail.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
Hi, Jason,
Mostly good to me, just a few nitpicks below.
On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> We introduce VTDBus structure as an intermediate step for searching
> the address space. This works well with SID based matching/lookup. But
> when we want to support SID plus PA
On Thu, Apr 21, 2022 at 11:51 PM Richard Henderson
wrote:
>
> On 4/20/22 16:46, Bin Meng wrote:
> > It seems you were trying to build every commit for bisectabliity? Is
> > there an easy way to do such automatically?
>
> git rebase --exec "cd build && make"
>
This works! Thanks Richard.
Regards,
On Fri, Apr 22, 2022 at 8:48 AM Alistair Francis
wrote:
> On Thu, Apr 21, 2022 at 12:17 PM Bin Meng wrote:
> >
> > On Wed, Apr 20, 2022 at 5:57 PM wrote:
> > >
> > > From: Frank Chang
> > >
> > > Allow user to set core's marchid, mvendorid, mipid CSRs through
> > > -cpu command line option.
>
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Create a platform bus to allow dynamic devices to be connected. This is
> based on the ARM implementation.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> include/hw/riscv/virt.h
On 4/21/22 10:31, Richard Henderson wrote:
The following changes since commit 401d46789410e88e9e90d76a11f46e8e9f358d55:
Merge tag 'pull-target-arm-20220421' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-21
08:04:43 -0700)
are available in the Git rep
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Similar to the ARM virt machine add support for adding device tree
> entries for dynamically created devices.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> hw/riscv/virt.c | 25
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Add support for plugging in devices, this was tested with the TPM
> device.
>
> Signed-off-by: Alistair Francis
> Reviewed-by: Edgar E. Iglesias
> ---
> hw/riscv/virt.c | 35 +
On Wed, Apr 20, 2022 at 1:53 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Imply the TPM sysbus devices. This allows users to add TPM devices to
> the RISC-V virt board.
>
> This was tested by first creating an emulated TPM device:
>
> swtpm socket --tpm2 -t -d --tpmstate dir=/tmp
On Mon, Apr 18, 2022 at 5:13 AM Ben Dooks wrote:
>
> Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify
> the code.
>
> Signed-off-by; Ben Dooks
; should be replaced to :
Not sure how you did that, but you can do with "git commit -s" and git
will take care of the SoB tag.
> ---
> hw/
On 2022/04/22 0:07, Christian Schoenebeck wrote:
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and chmod() respectively if S_IFSOCK
was passed with mode argument.
Link: https://lore.kernel.org/qemu-devel/17933734.zYzKuhC07K@silver/
Signed-off-by:
On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
wrote:
>
> Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> case, walk_pte will erroneously merge them.
>
> Enforce the split up, by tracking the virtual base address.
>
> Let's say we have the mapping:
> 0x8120 -> 0x89623000 (4
On Fri, Apr 22, 2022 at 10:53 AM Bin Meng wrote:
>
> On Tue, Apr 5, 2022 at 1:34 AM Ralf Ramsauer
> wrote:
> >
> > Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
> > case, walk_pte will erroneously merge them.
> >
> > Enforce the split up, by tracking the virtual base address
+Richard
On Wed, Apr 20, 2022 at 4:16 PM Bin Meng wrote:
>
> On Tue, Apr 12, 2022 at 9:11 AM Bin Meng wrote:
> >
> > On Thu, Mar 24, 2022 at 9:48 PM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > Sync uboot_image.h from upstream U-Boot v2022.01 release [1].
> > >
> > > [1] https://sour
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
On 4/21/22 11:40, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
The following changes since commit 28298069afff3eb696e4995e63b2579b27adf378:
Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into
staging (2022-04-21 09:27:54 -0700)
are available in the
Jag Raman writes:
>> On Apr 21, 2022, at 10:59 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Setup a handler to run vfio-user context. The context is driven by
>>> messages to the file descriptor associated with it - get the fd for
>>> the context and hook up the handler
Jag Raman writes:
>> On Apr 21, 2022, at 10:55 AM, Markus Armbruster wrote:
>>
>> Jagannathan Raman writes:
>>
>>> Add blocker to prevent hot-unplug of devices
>>
>> Why do you need this? I'm not doubting you do, I just want to read your
>> reasons here :)
>
> Hi Markus, :)
>
> The x-vfio-u
This add two addition test cases for accumulative mode under sg enabled.
The input vector was manually craft with "abc" + bit 1 + padding zeros + L.
The padding length depends on algorithm, i.e. SHA512 (1024 bit),
SHA256 (512 bit).
The result was calculated by command line sha512sum/sha256sum uti
The aspeed ast2600 accumulative mode is described in datasheet
ast2600v10.pdf section 25.6.4:
1. Allocating and initiating accumulative hash digest write buffer
with initial state.
* Since QEMU crypto/hash api doesn't provide the API to set initial
state of hash library, and the init
Support HACE28: Hash HMAC Key Buffer Base Address Register.
Signed-off-by: Troy Lee
Signed-off-by: Steven Lee
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 7 +++
include/hw/misc/aspeed_hace.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/misc/aspeed_hace.c b
This patch series implements ast2600 hace engine with accumulative mode
and unit test against to it.
Verified with following models
- AST2600 with OpenBmc VERSION_ID=2.12.0-dev-660-g4c7b3e692-dirty
- check hash verification in uboot and check whether qemu crashed
during openbmc web gui login
On Tue, Mar 8, 2022 at 10:28 PM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 10:15:49PM +0530, Ani Sinha wrote:
> >
> > Change log:
> > v2: rebased the patchset. Laine's response is appended at the end.
> >
> > I am re-introducing the patchset for which got
> > reverted here few months b
Coverity issues several UNINIT warnings against amd_iommu.c [1]. This
patch fixes them by clearing evt before encoding. On top of it, this
patch changes the event log size to 16 bytes per IOMMU specification,
and fixes the event log entry format in amdvi_encode_event().
[1] CID 1487116/1487200/148
On Fri, Apr 22, 2022 at 8:13 AM Peter Xu wrote:
>
> On Wed, Mar 30, 2022 at 04:36:36PM +0800, Jason Wang wrote:
> > > If not, do we want to apply this version scheme only when it
> > > reaches the production quality or also in the experimental phase?
> >
> > Yes. E.g if we think scalable mode is m
On Fri, Apr 22, 2022 at 9:17 AM Peter Xu wrote:
>
> Hi, Jason,
>
> Mostly good to me, just a few nitpicks below.
>
> On Mon, Mar 21, 2022 at 01:54:27PM +0800, Jason Wang wrote:
> > We introduce VTDBus structure as an intermediate step for searching
> > the address space. This works well with SID b
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