.., it will help with code readability and make easier
to extend method in followup patches
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 139 ---
1 file changed, 77 insertions(+), 62 deletions(-)
diff --git a/hw/i386/acpi-build.c
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 1 +
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 13 -
Signed-off-by: Igor Mammedov
---
tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
---
On 7/1/22 13:40, Francisco Iglesias wrote:
Hi Iris,
Looks good, a couple of minor comments below!
On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
Signed-off-by: Iris Chen
---
hw/block/m25p80.c | 74 +++
1 file changed, 62 insertions(+), 12
On Tue, 28 Jun 2022 at 05:35, Richard Henderson
wrote:
>
> Mark these as a non-streaming instructions, which should trap
stray "a".
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On 6/20/22 19:19, Daniel P. Berrangé wrote:
> Libvirt provides QMP passthrough APIs for the QEMU driver and these are
> exposed in virsh. It is not especially pleasant, however, using the raw
> QMP JSON syntax. QEMU has a tool 'qmp-shell' which can speak QMP and
> exposes a human friendly
HPET AML doesn't depend on piix4 nor q35, move code buiding it
to common scope to avoid duplication.
Signed-off-by: Igor Mammedov
---
hw/i386/acpi-build.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index
Reviewed-by: Leandro Lupori
Signed-off-by: Lucas Coutinho
---
target/ppc/helper.h | 2 +-
target/ppc/insn32.decode | 2 ++
target/ppc/mmu-hash64.c | 2 +-
target/ppc/translate.c | 14 --
This is a follow-up for commit 892a4f6a750a ("linux-user: Add partial
support for MADV_DONTNEED"), which added passthrough for anonymous
mappings. File mappings can be handled in a similar manner.
In order to do that, mark pages, for which mmap() was passed through,
with PAGE_PASSTHROUGH, and
Expected change:
+Device (SE8)
+{
+Name (_ADR, 0x001D) // _ADR: Address
+Name (ASUN, 0x1D)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific
Method
{
On Tue, 2022-06-28 at 15:21 +0200, Cornelia Huck wrote:
> On Tue, Jun 28 2022, Thomas Huth wrote:
>
> > Use VIRTIO_DASD_BLOCK_SIZE instead of the magic value 4096.
> >
> > Signed-off-by: Thomas Huth
> > ---
> > pc-bios/s390-ccw/virtio.h| 1 +
> > pc-bios/s390-ccw/virtio-blkdev.c | 2
There's a couple of places that seem to duplicate this calculation
of RAM size above the 4G boundary. Move all those to a helper function.
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git
On Fri, Jul 1, 2022 at 4:05 AM Hanna Reitz wrote:
>
> On 16.06.22 16:26, John Snow wrote:
> > In certain container environments we may not have FUSE at all, so skip
> > the test in this circumstance too.
> >
> > Signed-off-by: John Snow
> > ---
> > tests/qemu-iotests/108 | 5 +
> > 1 file
If flush is called when no buffer was sent with MSG_ZEROCOPY, it currently
returns 1. This return code should be used only when Linux fails to use
MSG_ZEROCOPY on a lot of sendmsg().
Fix this by returning early from flush if no sendmsg(...,MSG_ZEROCOPY)
was attempted.
Fixes: 2bc58ffc2926
At the start of pc_memory_init() we usually pass a range of
0..UINT64_MAX as pci_memory, when really its 2G (i440fx) or
32G (q35). To get the real user value, we need to get pci-host
passed property for default pci_hole64_size. Thus to get that,
create the qdev prior to memory init to better make
Rather than hardcoding the 4G boundary everywhere, introduce a
X86MachineState field @above_4g_mem_start and use it
accordingly.
This is in preparation for relocating ram-above-4g to be
dynamically start at 1T on AMD platforms.
Signed-off-by: Joao Martins
Reviewed-by: Igor Mammedov
---
On Fri, Jul 01, 2022 at 09:35:00AM -0400, Igor Mammedov wrote:
> HPET AML doesn't depend on piix4 nor q35, move code buiding it
> to common scope to avoid duplication.
>
> Signed-off-by: Igor Mammedov
Apropos, tests/data/acpi/rebuild-expected-aml.sh ignores the
fact that some tables might be
Factor out the calculation of the base address of the MR. It will be
used later on for the cxl range end counterpart calculation and as
well in pc_memory_init() CXL mr initialization, thus avoiding
duplication.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 28
This in preparation to allow pc_pci_hole64_start() to be called early
in pc_memory_init(), handle CXL memory region end when its underlying
memory region isn't yet initialized.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 13 +
1 file changed, 13
The added enforcing is only relevant in the case of AMD where the
range right before the 1TB is restricted and cannot be DMA mapped
by the kernel consequently leading to IOMMU INVALID_DEVICE_REQUEST
or possibly other kinds of IOMMU events in the AMD IOMMU.
Although, there's a case where it may
On Wed, Jun 29, 2022 at 7:18 PM Richard Henderson
wrote:
>
> On 6/29/22 13:45, Vladimir Sementsov-Ogievskiy wrote:
> > The following changes since commit ad4c7f529a279685da84297773b4ec8080153c2d:
> >
> >Merge tag 'pull-semi-20220628' of https://gitlab.com/rth7680/qemu into
> > staging
On Fri, Jul 01, 2022 at 12:56:19PM -0700, Peter Delevoryas wrote:
> This change moves the code that connects the SoC UART's to serial_hd's
> to the machine.
>
> It makes each UART a proper child member of the SoC, and then allows the
> machine to selectively initialize the chardev for each UART
Signed-off-by: Leonardo Bras
---
qapi/migration.json | 5 -
migration/migration.c | 1 +
monitor/hmp-cmds.c| 4
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index 7102e474a6..925f009868 100644
--- a/qapi/migration.json
+++
To support multiple SoC's running simultaneously, we need a unique name for
each RAM region. DRAM is created by the machine, but SRAM is created by the
SoC, since in hardware it is part of the SoC's internals.
We need a way to uniquely identify each SRAM region though, for VM
migration. Since
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The next patch is going to add more virtio-block specific code to
> virtio_blk_setup_device(), and if the virtio-scsi code is also in
> there, this is more cumbersome. And the calling function
> virtio_setup()
> in main.c looks at the device
Use the pre-initialized pci-host qdev and fetch the
pci-hole64-size into pc_memory_init() newly added argument.
piix needs a bit of care given all the !pci_enabled()
and that the pci_hole64_size is private to i440fx.
This is in preparation to determine that host-phys-bits are
enough and for
On Thu, Jun 30, 2022 at 11:22:31AM +0800, Jinhao Fan wrote:
> +static int nvme_init_sq_ioeventfd(NvmeSQueue *sq)
> +{
> +NvmeCtrl *n = sq->ctrl;
> +uint16_t offset = sq->sqid << 3;
> +int ret;
> +
> +ret = event_notifier_init(>notifier, 0);
> +if (ret < 0) {
> +return
It is assumed that the whole GPA space is available to be DMA
addressable, within a given address space limit, except for a
tiny region before the 4G. Since Linux v5.4, VFIO validates
whether the selected GPA is indeed valid i.e. not reserved by
IOMMU on behalf of some specific devices or
On Tue, 28 Jun 2022 at 05:40, Richard Henderson
wrote:
>
> We can reuse the SVE functions for implementing moves to/from
> horizontal tile slices, but we need new ones for moves to/from
> vertical tile slices.
>
> Signed-off-by: Richard Henderson
> ---
> diff --git a/target/arm/sme_helper.c
Move calculation of CXL memory region end to separate helper in
preparation to allow pc_pci_hole64_start() to be called before
any mrs are initialized.
Cc: Jonathan Cameron
Signed-off-by: Joao Martins
---
hw/i386/pc.c | 31 +--
1 file changed, 21 insertions(+), 10
On Thu, 30 Jun 2022 09:30:58 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jun 30, 2022 at 02:40:13PM +0200, Brice Goglin wrote:
> >
> > Le 30/06/2022 à 14:23, Igor Mammedov a écrit :
> > > On Thu, 30 Jun 2022 09:36:47 +0200
> > > Brice Goglin wrote:
> > >
> > > > Allow -numa without
Hi Mark,
On 6/29/22 14:39, Mark Cave-Ayland wrote:
> Here is the follow-on series from part 1 which completes the work to remove
> the legacy global device init functions for PS2 devices. Now that part 1 has
> been applied, the hard part to remove the PS2 function callback and argument
> has been
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also
The first patch avoid spuriously returning 1 [*] when zero-copy flush is
attempted before any buffer was sent using MSG_ZEROCOPY.
[*] zero-copy not being used, even though it's enabled and supported
by kernel
The second patch introduces a new migration stat (zero-copy-copied)
that will be used
Some errors, like the lack of Scatter-Gather support by the network
interface(NETIF_F_SG) may cause sendmsg(...,MSG_ZEROCOPY) to fail on using
zero-copy, which causes it to fall back to the default copying mechanism.
After each full dirty-bitmap scan there should be a zero-copy flush
happening,
v5[6] -> v6:
* Rebased to latest staging
* Consider @cxl_base setting to also use above_4g_mem_start (Igor Mammedov)
* Use 4 * GiB instead of raw hex (Igor Mammedov)
* Delete @host_type (Igor Mammedov)
* Rename to i440fx_dev to i440fx_host (Igor Mammedov)
* Rebase on top of patch that removes
Move obtaining hole64_start from device_memory MR base/size into an helper
alongside correspondent getters in pc_memory_init() when the hotplug
range is unitialized.
This is the final step that allows pc_pci_hole64_start() to be callable
at the beginning of pc_memory_init() before any MRs are
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The s390-ccw bios fails to boot if the boot disk is a virtio-blk
> disk with a sector size of 4096. For example:
>
> dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX
> fdasd -a /dev/dasdX
> install a guest onto /dev/dasdX1 using
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The virtio_assume_scsi() function is very questionable: First, it
> is only called for virtio-blk, and not for virtio-scsi, so the naming
> is already quite confusing. Second, it is called if we detected a
> "invalid" IPL disk, trying to fix
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> It looks nicer if we separate the run_ccw() from the IPL_assert()
> statement, and the error message should talk about "virtio device"
> instead of "block device", since this code is nowadays used for
> non-block (i.e. network) devices, too.
On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> Feature negotiation should be done first, since some fields in the
> config area can depend on the negotiated features and thus should
> rather be read afterwards.
>
> While we're at it, also adjust the error message here a little bit
> (the
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also
On Fri, Jul 1, 2022 at 5:37 AM Thomas Huth wrote:
> On 29/06/2022 08.28, Ani Sinha wrote:
> > On Tue, Jun 28, 2022 at 11:30 PM Michael S. Tsirkin wrote:
> >> On Tue, Jun 28, 2022 at 05:15:05PM +0100, Daniel P. Berrangé wrote:
> >>> FYI, the reason much of this is intentionally NOT under the
I added this helper in the Aspeed machine file a while ago to help
initialize fuji-bmc i2c devices. This moves it to the official pca954x
file so that other files can use it.
This does something very similar to pca954x_i2c_get_bus, but I think
this is useful when you have a very complicated dts
I noticed this error while building QEMU on Mac OS X:
[1040/1660] Compiling Objective-C object libcommon.fa.p/ui_cocoa.m.o
../ui/cocoa.m:803:17: warning: variable 'switched_to_fullscreen' set but
not used [-Wunused-but-set-variable]
static bool switched_to_fullscreen = false;
On 7/1/22 22:02, Peter Delevoryas wrote:
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should
Add to peter.mayd...@linaro.org
在 2022/7/1 11:07, Mao Bibo 写道:
> Loongarch pch msi intc connects to extioi controller, the range of irq number
> is 64-255. Here adds irqbase property for loongarch pch msi controller, we can
> get irq offset from view of pch_msi controller with the method:
> msi
On 7/1/22 10:34, Lucas Coutinho wrote:
Resent after rebasing and fixing conflicts with master.
Add Leandro Lupori as reviewer.
Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br>
Implement the following PowerISA v3.0 instuction:
slbiag: SLB Invalidate All Global X-form
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