在 2023/2/15 11:35, Zhao Liu 写道:
On Wed, Feb 15, 2023 at 10:36:34AM +0800, wangyanan (Y) wrote:
Date: Wed, 15 Feb 2023 10:36:34 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 02/18] tests: Rename test-x86-cpuid.c to
test-x86-apicid.c
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
smp command has the "clusters" parameter but x86 hasn't supported that
level. Though "clusters" was introduced to help define L2 cache topology
[1], using cluster to define x86's L2 cache topology will cause the
compatibility problem:
Well,
On Feb 15 12:01, Major Saheb wrote:
> > Assuming you are *not* explicitly configuring shadow doorbells, then I
> > think you might have a broken driver that does not properly reset the
> > controller before using it (are you tripping CC.EN?). That could explain
> > the admin queue size of 32
Avihai Horon wrote:
> Add new function qemu_file_get_to_fd() that allows reading data from
> QEMUFile and writing it straight into a given fd.
>
> This will be used later in VFIO migration code.
>
> Signed-off-by: Avihai Horon
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: Cédric Le
On 15/02/2023 08.10, Philippe Mathieu-Daudé wrote:
On 15/2/23 06:48, Thomas Huth wrote:
We are not on a hot path here, so there is no real need for the logic
here with the split heap and stack space allocation. Simplify it by
always allocating memory from the heap.
Suggested-by: Philippe
John Snow writes:
> Pylint under 3.6 does not believe that Collection is subscriptable at
> runtime. It is, making this a Pylint
> bug. https://github.com/PyCQA/pylint/issues/2377
>
> They closed it as fixed, but that doesn't seem to be true as of Pylint
> 2.13.9, the latest version you can
On 14/2/23 19:49, Richard Henderson wrote:
On 2/14/23 00:18, Philippe Mathieu-Daudé wrote:
__attribute__((nonnull)) void a1(void *ptr)
{
// can no use assert(ptr) because compiler warning
}
I briefly glossed over that...
I realize we'd probably want to add
On 15/2/23 06:48, Thomas Huth wrote:
We are not on a hot path here, so there is no real need for the logic
here with the split heap and stack space allocation. Simplify it by
always allocating memory from the heap.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
在 2023/2/15 15:10, Zhao Liu 写道:
On Wed, Feb 15, 2023 at 11:28:25AM +0800, wangyanan (Y) wrote:
Date: Wed, 15 Feb 2023 11:28:25 +0800
From: "wangyanan (Y)"
Subject: Re: [PATCH RESEND 05/18] i386/cpu: Consolidate the use of
topo_info in cpu_x86_cpuid()
在 2023/2/13 17:36, Zhao Liu 写道:
From:
On Wed, Feb 15, 2023 at 11:28:25AM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 11:28:25 +0800
> From: "wangyanan (Y)"
> Subject: Re: [PATCH RESEND 05/18] i386/cpu: Consolidate the use of
> topo_info in cpu_x86_cpuid()
>
> 在 2023/2/13 17:36, Zhao Liu 写道:
> > From: Zhao Liu
> >
> > In
On x86, there are two notifiers registered due to vtd-ir memory region
splitting the whole address space. During replay of the address space
for each notifier, the whole address space is scanned which is
unnecessory.
We only need to scan the space belong to notifier montiored space.
Assert when
Cédric Le Goater writes:
> Hello,
>
> This series starts with a first set of patches fixing I2C slave mode
> in the Aspeed I2C controller, a test device and its associated test in
> avocado.
>
> Follow some cleanups which allow the use of block devices instead of
> drives. So that, instead of
> Assuming you are *not* explicitly configuring shadow doorbells, then I
> think you might have a broken driver that does not properly reset the
> controller before using it (are you tripping CC.EN?). That could explain
> the admin queue size of 32 (default admin queue depth for the Linux nvme
>
On 2023/2/9 14:23, Deepak Gupta wrote:
Implementation for forward cfi and backward cfi needs helper function
to determine if currently fcfi and bcfi are enabled. Enable depends on
privilege mode and settings in sstatus/menvcfg/henvcfg/mseccfg CSRs.
Signed-off-by: Deepak Gupta
Signed-off-by:
I don't find the modification for read_mstatus.
Zhiwei
On 2023/2/15 13:47, LIU Zhiwei wrote:
On 2023/2/9 14:23, Deepak Gupta wrote:
CSR_SSP and CSR_LPLR are new CSR additions to cpu/hart. This patch
allows
access to these CSRs. A predicate routine handles access to these CSR as
per
On 2023/2/9 14:24, Deepak Gupta wrote:
zisslpcfi's forward cfi if enabled on a hart, enables tracking of
indirect branches. CPU/hart internally keeps a state `elp` short
for expecting landing pad instruction. This state goes into
LP_EXPECTED on an indirect branch. But an interrupt/exception
On Tue, Feb 14, 2023 at 2:16 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/13/23 14:27, Warner Losh wrote:
> > +/*
> > + * Convert the old value from host to target.
>
> host vs guest is clearer language; "target" gets overloaded, even though
> still present in
> the code
On 15/02/2023 06.20, Thomas Huth wrote:
On 14/02/2023 15.58, Philippe Mathieu-Daudé wrote:
On 14/2/23 15:10, Thomas Huth wrote:
"note_size" can be smaller than sizeof(note), so unconditionally calling
memset(notep, 0, sizeof(note)) could cause a memory corruption here in
case notep has been
We are not on a hot path here, so there is no real need for the logic
here with the split heap and stack space allocation. Simplify it by
always allocating memory from the heap.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
Based-on:
On 2023/2/9 14:23, Deepak Gupta wrote:
CSR_SSP and CSR_LPLR are new CSR additions to cpu/hart. This patch allows
access to these CSRs. A predicate routine handles access to these CSR as
per specification.
This patch also implments new bit definitions in menvcfg/henvcfg/mstatus/
sstatus CSRs
On 14/02/2023 15.58, Philippe Mathieu-Daudé wrote:
On 14/2/23 15:10, Thomas Huth wrote:
"note_size" can be smaller than sizeof(note), so unconditionally calling
memset(notep, 0, sizeof(note)) could cause a memory corruption here in
case notep has been allocated dynamically, thus let's use
Ok, will do that.
On Tue, Feb 14, 2023 at 12:35 PM Cédric Le Goater wrote:
> Hello,
>
> [ adding the lists ]
>
> > > +static void fb_bmc_i2c_init(AspeedMachineState *bmc)
> >
> > The same routine name is proposed in the tiogapass patch :
> >
> >
>
On 2023/2/9 14:23, Deepak Gupta wrote:
`zisslpcfi` extension adds two new CSRs. CSR_SSP and CSR_LPLR.
- CSR_SSP: This CSR holds shadow stack pointer for current privilege mode
CSR_SSP is accessible in all modes. Each mode must establish
it's own CSR_SSP.
- CSR_LPLR:
On Wed, Feb 15, 2023 at 10:58:07AM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 10:58:07 +0800
> From: "wangyanan (Y)"
> Subject: Re: [PATCH RESEND 03/18] softmmu: Fix CPUSTATE.nr_cores'
> calculation
>
> Hi Zhao,
>
> 在 2023/2/13 17:36, Zhao Liu 写道:
> > From: Zhuocheng Ding
> >
> >
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores/cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of
On Wed, Feb 15, 2023 at 10:36:34AM +0800, wangyanan (Y) wrote:
> Date: Wed, 15 Feb 2023 10:36:34 +0800
> From: "wangyanan (Y)"
> Subject: Re: [PATCH RESEND 02/18] tests: Rename test-x86-cpuid.c to
> test-x86-apicid.c
>
> 在 2023/2/13 17:36, Zhao Liu 写道:
> > From: Zhao Liu
> >
> > In fact, this
On Tue, Feb 14, 2023 at 07:23:37PM +0800, wangyanan (Y) wrote:
> Date: Tue, 14 Feb 2023 19:23:37 +0800
> From: "wangyanan (Y)"
> Subject: Re: [RFC 06/52] hw/cpu: Introduce hybrid CPU topology
>
> 在 2023/2/14 18:16, Zhao Liu 写道:
> > On Mon, Feb 13, 2023 at 09:18:05PM +0800, wangyanan (Y) wrote:
>
On Tue, Feb 14, 2023 at 10:27:53AM +0100, Philippe Mathieu-Daudé wrote:
> Date: Tue, 14 Feb 2023 10:27:53 +0100
> From: Philippe Mathieu-Daudé
> Subject: Re: [RFC 06/52] hw/cpu: Introduce hybrid CPU topology
>
> On 14/2/23 10:30, Zhao Liu wrote:
> > On Mon, Feb 13, 2023 at 02:10:17PM +0100,
On Tue, Feb 14, 2023 at 11:40:14AM +0800, Mi, Dapeng1 wrote:
> Date: Tue, 14 Feb 2023 11:40:14 +0800
> From: "Mi, Dapeng1"
> Subject: RE: [RFC 25/52] mips: Replace MachineState.smp access with
> topology helpers
>
> > From: Zhao Liu
> > Sent: Monday, February 13, 2023 5:50 PM
> > To: Eduardo
>-Original Message-
>From: Peter Xu
>Sent: Wednesday, February 15, 2023 1:29 AM
>To: Duan, Zhenzhong
>Cc: Jason Wang ; qemu-devel@nongnu.org;
>m...@redhat.com; pbonz...@redhat.com; richard.hender...@linaro.org;
>edua...@habkost.net; marcel.apfelb...@gmail.com; da...@redhat.com;
Hi Zhao,
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhuocheng Ding
>From CPUState.nr_cores' comment, it represents "number of cores within
this CPU package".
After 003f230 (machine: Tweak the order of topology members in struct
CpuTopology), the meaning of smp.cores changed to "the number of
On 2023/2/15 10:22, Bin Meng wrote:
On Tue, Feb 14, 2023 at 10:59 PM weiwei wrote:
On 2023/2/14 22:27, Bin Meng wrote:
At present the envcfg CSRs predicate() routines are generic one like
smode(), hmode. The configuration check is done in the read / write
routine. Create a new predicate
On 2023/2/9 14:23, Deepak Gupta wrote:
Introducing riscv `zisslpcfi` extension to riscv target. `zisslpcfi`
extension provides hardware assistance to riscv hart to enable control
flow integrity (CFI) for software.
`zisslpcfi` extension expects hart to implement `zimops`. `zimops` stands
for
On Tue, Feb 14, 2023 at 10:17:45AM +0800, Mi, Dapeng1 wrote:
> Date: Tue, 14 Feb 2023 10:17:45 +0800
> From: "Mi, Dapeng1"
> Subject: RE: [RFC 22/52] riscv: Replace MachineState.smp access with
> topology helpers
>
> > From: Zhao Liu
> > Sent: Monday, February 13, 2023 5:50 PM
> > To: Eduardo
On Tue, Feb 14, 2023 at 09:46:50AM +0800, wangyanan (Y) wrote:
> Date: Tue, 14 Feb 2023 09:46:50 +0800
> From: "wangyanan (Y)"
> Subject: Re: [RFC 42/52] hw/machine: Add hybrid_supported in generic topo
> properties
>
> Hi Zhao,
>
> 在 2023/2/13 17:50, Zhao Liu 写道:
> > From: Zhao Liu
> >
> >
在 2023/2/13 17:36, Zhao Liu 写道:
From: Zhao Liu
In fact, this unit tests APIC ID other than CPUID.
Rename to test-x86-apicid.c to make its name more in line with its
actual content.
Signed-off-by: Zhao Liu
---
MAINTAINERS| 2 +-
On Tue, Feb 14, 2023 at 09:14:13AM +0800, Mi, Dapeng1 wrote:
> Date: Tue, 14 Feb 2023 09:14:13 +0800
> From: "Mi, Dapeng1"
> Subject: RE: [RFC 09/52] hw/machine: Introduce core type for hybrid topology
>
> > From: Zhao Liu
> > Sent: Monday, February 13, 2023 5:50 PM
> > To: Eduardo Habkost ;
On Tue, Feb 14, 2023 at 09:12:11AM +0800, Mi, Dapeng1 wrote:
> Date: Tue, 14 Feb 2023 09:12:11 +0800
> From: "Mi, Dapeng1"
> Subject: RE: [RFC 08/52] machine: Add helpers to get cpu topology info from
> MachineState.topo
>
> > From: Zhao Liu
> > Sent: Monday, February 13, 2023 5:50 PM
> > To:
On Tue, Feb 14, 2023 at 10:59 PM weiwei wrote:
>
>
> On 2023/2/14 22:27, Bin Meng wrote:
> > At present the envcfg CSRs predicate() routines are generic one like
> > smode(), hmode. The configuration check is done in the read / write
> > routine. Create a new predicate routine to cover such
On Mon, Feb 13, 2023 at 01:41:19PM +, Daniel P. Berrangé wrote:
> Date: Mon, 13 Feb 2023 13:41:19 +
> From: "Daniel P. Berrangé"
> Subject: Re: [RFC 04/52] i386/WHPX: Fix error message when fail to set
> ProcessorCount
>
> On Mon, Feb 13, 2023 at 05:49:47PM +0800, Zhao Liu wrote:
> >
The V extension supports all vector load and store instructions except
the V extension does not support EEW=64 for index values when XLEN=32.
(Section 18.3)
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc |
Only V extension supports EEW = 64 in these cases: Zve64* extensions don't
support EEW = 64 in these cases as commented before the check.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 3 +--
Add check for Zvfh and Zvfhmin.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c5c60d9e4d..e9832ea544 100644
---
Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c
Expose Zve64d,Zvfh,Zvfhmin properties.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 44abadc811..9d309b1a7f 100644
---
Add dependence chain:
* V => Zve64d => Zve64f => Zve32f => F
* V => Zve64d => D
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
Fix indent problems in vector related check.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/riscv/cpu.c
Zvfh supports vector float point instructions with SEW = 16
and supports conversions between 8-bit integers and binary16 values.
Zvfhmin supports vfwcvt.f.f.v and vfncvt.f.f.w instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
Specification for Zv* extensions can be found in:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zvfh-upstream-v2
v2:
* improve the error message for vector related check suggested by Daniel
Henrique
Check for Zve32f/Zve64d can overlap check for F/D.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
will be enabled when Zhinx is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 128
1 file changed, 21 insertions(+), 107 deletions(-)
Add properties for Zve64d,Zvfh,Zvfhmin extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..54c6875617
We needn't check Zfh and Zhinx in these instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvzfh.c.inc | 25 +++
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git
We can remove this alias as it only has two usages now, and no longer
pays for the confusion of "yet another type".
Signed-off-by: John Snow
---
scripts/qapi/expr.py | 13 +++--
scripts/qapi/parser.py | 5 ++---
2 files changed, 5 insertions(+), 13 deletions(-)
diff --git
New versions of flake8 don't like same-line comments. (It's a version
newer than what fc37 ships, but it still makes my life easier to fix it
now.)
Signed-off-by: John Snow
Reviewed-by: Markus Armbruster
---
scripts/qapi/.flake8 | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Pylint under 3.6 does not believe that Collection is subscriptable at
runtime. It is, making this a Pylint
bug. https://github.com/PyCQA/pylint/issues/2377
They closed it as fixed, but that doesn't seem to be true as of Pylint
2.13.9, the latest version you can install under Python 3.6. 2.13.9
This patch creates a new type, QAPIExpression, which represents a parsed
expression complete with QAPIDoc and QAPISourceInfo.
This patch turns parser.exprs into a list of QAPIExpression instead,
and adjusts expr.py to match.
This allows the types we specify in parser.py to be "remembered" all
Newer versions of pylint disable the "no-self-use" message by
default. Older versions don't, though. If we leave the suppressions in,
pylint yelps about useless options. Just tell pylint to shush.
Signed-off-by: John Snow
Reviewed-by: Markus Armbruster
---
scripts/qapi/pylintrc | 1 +
1 file
This is part five (c), and focuses on sharing strict types between
parser.py and expr.py.
gitlab: https://gitlab.com/jsnow/qemu/-/commits/python-qapi-cleanup-pt5c
Every commit should pass with:
- `isort -c qapi/`
- `flake8 qapi/`
- `pylint --rcfile=qapi/pylintrc qapi/`
- `mypy
With the two major JSON-ish type hierarchies clarified for distinct
purposes; QAPIExpression for parsed expressions and JSONValue for
introspection data, remove this FIXME as no longer an action item.
A third JSON-y data type, _ExprValue, is not meant to represent JSON in
the abstract but rather
On Tue, 14 Feb 2023, Peter Maydell wrote:
> On Mon, 13 Feb 2023 at 22:34, Stefano Stabellini
> wrote:
> >
> > On Mon, 13 Feb 2023, Peter Maydell wrote:
> > > On Fri, 10 Feb 2023 at 22:27, Stefano Stabellini
> > > wrote:
> > > >
> > > > The following changes since commit
> > > >
From: Vikram Garhwal
Add a new machine xenpvh which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
From: Vikram Garhwal
Replace g_malloc with g_new and perror with error_report.
Signed-off-by: Vikram Garhwal
Reviewed-by: Stefano Stabellini
Reviewed-by: Paul Durrant
---
hw/xen/xen-hvm-common.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: Vikram Garhwal
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common
From: Vikram Garhwal
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move
From: Vikram Garhwal
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index a76c855312..8292cdcec5 100644
--- a/meson.build
+++
The following changes since commit 6a50f64ca01d0a7b97f14f069762bfd88160f31e:
Merge tag 'pull-request-2023-02-14' of https://gitlab.com/thuth/qemu into
staging (2023-02-14 14:46:10 +)
are available in the Git repository at:
https://gitlab.com/sstabellini/qemu xenpvh2
for you to fetch
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated
On 2/14/23 09:42, Fabiano Rosas wrote:
@@ -310,8 +313,8 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
g_string_append_printf(s, "", base_reg++);
-info->num += 2;
+/* Define the predicate registers. */
for (i = 0; i < 16; i++) {
There's a info->num++; at
On 2/13/23 14:27, Warner Losh wrote:
Most of the time, it's useful to make our best effort, but sometimes we
want to know right away when we don't implement something. First place
we use it is for unknown syscalls.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-syscall.c | 4
On 2/13/23 14:27, Warner Losh wrote:
+oidplen = sizeof(oid) / sizeof(int);
ARRAY_SIZE(oid)
Otherwise,
Reviewed-by: Richard Henderson
r~
On 2/13/23 14:27, Warner Losh wrote:
+int32_t *snamep = g_malloc(sizeof(int32_t) * namelen), *p, *q, i;
g_new(int32_t, namelen)
+unlock_user(holdp, oldp, holdlen);
+unlock_user(holdp, oldp, ret == 0 ? holdlen : 0);
double-unlock. clearly the first line is extra.
Otherwise,
On 2/14/23 11:31, Warner Losh wrote:
Right now they aren't used at all for ABI64... But that's in later patches...
We only do
special things for LONG or ULONG on ABI32... Otherwise, the normal paths
wouldn't
call these at all.
Yes, I've just seen patch 9, and agree they aren't needed for
On 2/13/23 14:27, Warner Losh wrote:
+case HW_NCPU:
+if (oldlen) {
+(*(int32_t *)holdp) = tswap32(bsd_get_ncpu());
+}
+holdlen = sizeof(int32_t);
+ret = 0;
+goto out;
Anything using SYSCTL_INT should use
On Tue, Feb 14, 2023 at 1:52 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/13/23 14:27, Warner Losh wrote:
> > +#ifdef TARGET_ABI32
> > +/*
> > + * Limit the amount of available memory to be most of the 32-bit address
> > + * space. 0x100c000 was arrived at through trial and
On Sun, 12 Feb 2023 17:36:49 +0200
Avihai Horon wrote:
> On 27/01/2023 23:11, Alex Williamson wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Thu, 26 Jan 2023 20:49:35 +0200
> > Avihai Horon wrote:
> >
> >> There are already two places where dirty page
On 2/13/23 14:27, Warner Losh wrote:
From: Juergen Lock
do_freebsd_sysctl_oid filters out some of the binary and special sysctls
where host != target. None of the sysctls that have to be translated from
host to target are handled here.
Signed-off-by: Juergen Lock
Co-Authored-by: Stacey Son
On 2/13/23 14:27, Warner Losh wrote:
From: Juergen Lock
Helper functions for sysctl implementations. sysctl_name2oid and
sysctl_oidfmt convert oids between host and targets
Signed-off-by: Juergen Lock
Reviewed-by: Warner Losh
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-sys.c | 18
On 2/13/23 14:27, Warner Losh wrote:
+/*
+ * Convert the old value from host to target.
host vs guest is clearer language; "target" gets overloaded, even though still present in
the code base.
+ *
+ * For LONG and ULONG on ABI32, we need to 'down convert' the 8 byte quantities
+ * to 4
On 14/02/2023 20.14, Alexander Bulekov wrote:
On 230214 2009, Thomas Huth wrote:
On 14/02/2023 17.08, Philippe Mathieu-Daudé wrote:
On 14/2/23 16:38, Stefan Hajnoczi wrote:
On Sat, Feb 04, 2023 at 11:29:41PM -0500, Alexander Bulekov wrote:
Hello,
This series removes fork-based fuzzing.
How
Il mar 14 feb 2023, 18:26 Kevin Wolf ha scritto:
> Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben:
> > In the case of Python the issue is not the interpreter per se, though
> > there are a couple new feature in Python 3.7 that are quite nice (for
> > example improved data classes[1] or
On 2/13/23 14:27, Warner Losh wrote:
+#ifdef TARGET_ABI32
+/*
+ * Limit the amount of available memory to be most of the 32-bit address
+ * space. 0x100c000 was arrived at through trial and error as a good
+ * definition of 'most'.
+ */
+static const abi_ulong target_max_mem = UINT32_MAX -
On 2/13/23 14:27, Warner Losh wrote:
From: Stacey Son
oidfmt uses undocumented system call to get the type of the sysctl.
Co-Authored-by: Sean Bruno
Signed-off-by: Sean Bruno
Co-Authored-by: Juergen Lock
Signed-off-by: Juergen Lock
Co-Authored-by: Raphael Kubo da Costa
Signed-off-by: Raphael
Hi, all.
In the future, there would be eBPF RSS + the helper for Libvirt interaction.
And those patches are required for future work. Technically they are
required for the current builds with linked libbpf 1.01.
Can we apply this patch?
On Wed, Dec 28, 2022 at 6:19 PM Andrew Melnichenko wrote:
On 13.01.23 14:29, Kevin Wolf wrote:
Another thing that could be tried is making failure in .bdrv_close less
likely by doing things earlier. At least ENOSPC could probably be
avoided if dirty bitmaps clusters were allocated during the write
request that first sets a bit in them (I know too
Richard Henderson writes:
> Signed-off-by: Richard Henderson
> ---
> target/arm/gdbstub64.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
> index 8d174ff6e0..02a0256c5c 100644
> --- a/target/arm/gdbstub64.c
> +++
On 13/02/2023 16:01, Vladimir Sementsov-Ogievskiy wrote:
To be used in further patch to identify the device hot-plugged into
pcie-root-port.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Anton Kuchin
---
include/hw/pci/pci.h | 1 +
hw/pci/pci.c | 33
Richard Henderson writes:
> Rather than increment base_reg and num, compute num
> from the change to base_reg at the end. Clean up some
> nearby comments.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/gdbstub64.c | 26 --
> 1 file changed, 16 insertions(+),
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
It should be zero, the only valid values are ON, OFF and BLINK.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Anton Kuchin
---
hw/pci/pcie.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pci/pcie.c
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
In pcie_cap_slot_write_config() we check for PCI_EXP_SLTCTL_PWR_OFF in
a bad form. We should distinguish PCI_EXP_SLTCTL_PWR which is a "mask"
and PCI_EXP_SLTCTL_PWR_OFF which is value for that mask.
Better code is in
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
*_by_mask() helpers shouldn't be used here (and that's the only one).
*_by_mask() helpers do shift their value argument, but in pcie.c code
we use values that are already shifted appropriately.
Happily, PCI_EXP_SLTCTL_PWR_ON is zero, so
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
The structure type is unused. Also, it's the only user of corresponding
macros, so drop them too.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Kuchin
---
include/hw/pci/pcie.h
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
We already have indicator values in
include/standard-headers/linux/pci_regs.h , no reason to reinvent them
in include/hw/pci/pcie_regs.h. (and we already have usage of
PCI_EXP_SLTCTL_PWR_IND_BLINK and PCI_EXP_SLTCTL_PWR_IND_OFF in
On 13/02/2023 16:00, Vladimir Sementsov-Ogievskiy wrote:
PCI_EXP_SLTCTL_PIC_OFF is a value, and PCI_EXP_SLTCTL_PIC is a mask.
Happily PCI_EXP_SLTCTL_PIC_OFF is a maximum value for this mask and is
equal to the mask itself. Still the code looks like a bug. Let's make
it more reader-friendly.
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