On 1/15/2024 1:59 PM, Zhao Liu wrote:
(Also cc "machine core" maintainers.)
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:18:17PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 12:18:17 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
On 1/15/2024
On Fri, Jan 12, 2024 at 07:05:07AM -0800, Steve Sistare wrote:
> Move common code for the error path in migrate_fd_connect to a shared
> fail label. No functional change.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
One nitpick below:
> ---
> migration/migration.c | 22
On Fri, Jan 12, 2024 at 07:05:10AM -0800, Steve Sistare wrote:
> Allow cpr-reboot for vfio if the guest is in the suspended runstate. The
> guest drivers' suspend methods flush outstanding requests and re-initialize
> the devices, and thus there is no device state to save and restore. The
> user
On LoongArch kvm mode if transparent huge page wants to be enabled, base
address and size of memslot from both HVA and GPA view. And LoongArch
supports both 4K and 16K page size with Linux kernel, so transparent huge
page size is calculated from real page size rather than hardcoded size.
When compiling qemu with system KVM mode for LoongArch, header files in
directory linux-headers/asm-loongarch should be used firstly. Otherwise it
fails to find kvm.h on system with old glibc, since latest kernel header
files are not installed.
This patch adds linux_arch definition for LoongArch
Hi, Palmer,
On Fri, Jan 12, 2024 at 10:03 PM Palmer Dabbelt wrote:
>
> On Fri, 12 Jan 2024 12:57:22 PST (-0800), r...@rivosinc.com wrote:
> > Commit f4e1168198 (linux-user: Split out host_sig{segv,bus}_handler)
> > introduced a bug, when returning from host_sigbus_handler the PC is
>
> So we
On 1/15/2024 2:35 PM, Zhao Liu wrote:
On Mon, Jan 15, 2024 at 02:11:17PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 14:11:17 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
On 1/15/2024 2:12 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15,
When running with TCI, the boot-serial-test can take longer than 3 minutes:
https://gitlab.com/qemu-project/qemu/-/jobs/5890481086#L4774
Bump the timeout to 4 minutes to avoid CI failures here.
Signed-off-by: Thomas Huth
---
tests/qtest/meson.build | 2 +-
1 file changed, 1 insertion(+), 1
Thank you.
Please see comments inline.
On Fri, Jan 12, 2024 at 7:03 PM Peter Maydell wrote:
On Tue, 9 Jan 2024 at 12:45, Shlomo Pongratz wrote:
Hi; thanks for this patch.
Hanlde wrap around caused by the fact that perior to version 460A
Is this "460A" version number a version of the
On Mon, Jan 15, 2024 at 02:57:30PM +0800, Yuan Yao wrote:
> Date: Mon, 15 Jan 2024 14:57:30 +0800
> From: Yuan Yao
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> On Mon, Jan 15, 2024 at 02:20:20PM +0800, Zhao Liu wrote:
> > On Mon, Jan 15, 2024 at 01:20:22PM +0800,
On 1/13/24 21:16, Alex Bennée wrote:
Pierrick Bouvier writes:
On 1/12/24 21:20, Alex Bennée wrote:
Pierrick Bouvier writes:
On 1/11/24 19:57, Philippe Mathieu-Daudé wrote:
Hi Pierrick,
On 11/1/24 15:23, Pierrick Bouvier wrote:
For now, it simply performs instruction, bb and mem count,
The test_prescaler() part in the npcm7xx_watchdog_timer test is quite
repetive, testing all possible combinations of the WTCLK and WTIS
bitfields. Since each test spins up a new instance of QEMU, this is
rather an expensive test, especially on loaded host systems.
For the normal quick test mode,
> On 04-Jan-2024, at 6:14 AM, Hao Xiang wrote:
>
> From: Juan Quintela
>
> This implements the zero page dection and handling.
>
> Signed-off-by: Juan Quintela
> ---
> migration/multifd.c | 41 +++--
> migration/multifd.h | 5 +
> 2 files changed, 44
On 1/15/2024 2:25 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:25:19PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 12:25:19 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode
CPUID[4]
On 1/15/2024 11:40 AM, Zhao Liu wrote:
On Mon, Jan 15, 2024 at 02:20:20PM +0800, Zhao Liu wrote:
> On Mon, Jan 15, 2024 at 01:20:22PM +0800, Yuan Yao wrote:
> > Date: Mon, 15 Jan 2024 13:20:22 +0800
> > From: Yuan Yao
> > Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
> >
> > Ah, so my understanding is
On Fri, Jan 12, 2024 at 07:05:03AM -0800, Steve Sistare wrote:
> bool migration_in_incoming_postcopy(void)
> diff --git a/ui/spice-core.c b/ui/spice-core.c
> index b3cd229..e43a93f 100644
> --- a/ui/spice-core.c
> +++ b/ui/spice-core.c
> @@ -580,7 +580,7 @@ static int
> On 04-Jan-2024, at 6:14 AM, Hao Xiang wrote:
>
> 1. Refactor multifd_send_thread function.
> 2. Implement buffer_is_zero_use_cpu to handle CPU based zero page
> checking.
> 3. Introduce the batch task structure in MultiFDSendParams.
>
> Signed-off-by: Hao Xiang
> ---
> include/qemu/dsa.h
Thank you.
Yes, with those two patches applied I have compiled qemu on Solaris 11.4
running on a SPARC-T4-1 (sun4v) system to emulate a single target: an HP
PA-RISC.
> On Jan 14, 2024, at 8:35 PM, Peter Xu wrote:
>
> On Thu, Jan 11, 2024 at 01:20:17PM -0500, Nick Briggs wrote:
>> Solaris has
On Fri, Jan 12, 2024 at 07:05:02AM -0800, Steve Sistare wrote:
> Change all migration notifiers to type NotifierWithReturn, so notifiers
> can return an error status in a future patch. For now, pass NULL for the
> notifier error parameter, and do not check the return value.
>
> Signed-off-by:
On Fri, Jan 12, 2024 at 07:05:01AM -0800, Steve Sistare wrote:
> Remove the error object from opaque data passed to notifiers.
> Use the new error parameter passed to the notifier instead.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jan 12, 2024 at 07:05:00AM -0800, Steve Sistare wrote:
> Pass an error object as the third parameter to "notifier with return"
> notifiers, so clients no longer need to bundle an error object in the
> opaque data. The new parameter is used in a later patch.
>
> Signed-off-by: Steve
A later commit requires one extra step to retrieve misa_mxl_max. As
misa_mxl is semantically more correct and does not need such a extra
step, refer to misa_mxl instead. Below is the explanation why misa_mxl
is more semantically correct to refer to than misa_mxl_max in this case.
Currently
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 21
15.01.2024 05:08, guoguangyao :
When closing PCREL, qemu-system-x86_64 run into error.
Eip modification here leads to the result. Using s->pc
in func gen_update_eip_next() solves the problem.
Fixes: b5e0d5d22fbf("target/i386: Fix 32-bit wrapping of pc/eip computation")
Signed-off-by:
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki
Acked-by: LIU Zhiwei
Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
---
target/riscv/tcg/tcg-cpu.c | 15 +++
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 4 +-
target/riscv/cpu.c | 162 -
Ping
On Sun, Jan 7, 2024 at 7:53 PM Hyman Huang wrote:
> v2:
> - rebase on master
> - add a commit to sort the error message so that an explanation
> error number can be returned on all failure paths
>
> Hyman Huang (2):
> i386/sev: Sort the error message
> i386/sev: Nitpick at the error
On Mon, Jan 15, 2024 at 02:11:17PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 14:11:17 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> On 1/15/2024 2:12 PM, Zhao Liu wrote:
> > Hi Xiaoyao,
> >
> > On Mon, Jan 15, 2024 at 12:34:12PM
On Thu, Jan 11, 2024 at 03:38:31PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Nov 27, 2023 at 05:25:42PM -0300, Fabiano Rosas wrote:
> >> Hi,
> >>
> >> In this v3:
> >>
> >> Added support for the "file:/dev/fdset/" syntax to receive multiple
> >> file descriptors. This allows
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:25:19PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 12:25:19 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode
> CPUID[4]
>
> On 1/15/2024 11:40 AM, Zhao Liu wrote:
> > > > +{
> > > > +uint32_t
On 1/15/2024 2:12 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:34:12PM +0800, Xiaoyao Li wrote:
Date: Mon, 15 Jan 2024 12:34:12 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
Yes, I think it's time to move to default 0x1f.
we
On Mon, Jan 15, 2024 at 01:20:22PM +0800, Yuan Yao wrote:
> Date: Mon, 15 Jan 2024 13:20:22 +0800
> From: Yuan Yao
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> Ah, so my understanding is incorrect on this.
>
> I tried on one raptor lake i5-i335U, which also
> On 04-Jan-2024, at 6:14 AM, Hao Xiang wrote:
>
> From: Juan Quintela
>
> We have to enable it by default until we introduce the new code.
>
> Signed-off-by: Juan Quintela
> ---
> migration/options.c | 15 +++
> migration/options.h | 1 +
> qapi/migration.json | 8 +++-
> 3
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:34:12PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 12:34:12 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> > Yes, I think it's time to move to default 0x1f.
>
> we don't need to do so until
Thank you.
Please see comments inline.
On Fri, Jan 12, 2024 at 7:03 PM Peter Maydell wrote:
>
> On Tue, 9 Jan 2024 at 12:45, Shlomo Pongratz wrote:
>
> Hi; thanks for this patch.
>
> > Hanlde wrap around caused by the fact that perior to version 460A
>
> Is this "460A" version number a version
Hi!
On 12/01/2024 18.05, Inès Varhol wrote:
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
Maybe add a short patch description (e.g. saying what aspects of the GPIOs
are tested here)?
diff --git a/tests/qtest/stm32l4x5_gpio-test.c
b/tests/qtest/stm32l4x5_gpio-test.c
new
(Also cc "machine core" maintainers.)
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 12:18:17PM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 12:18:17 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
>
> On 1/15/2024 11:27 AM, Zhao Liu wrote:
> > On
On Mon, Jan 15, 2024 at 12:34:12PM +0800, Xiaoyao Li wrote:
> On 1/15/2024 12:09 PM, Zhao Liu wrote:
> > Hi Yuan,
> >
> > On Mon, Jan 15, 2024 at 11:25:24AM +0800, Yuan Yao wrote:
> > > Date: Mon, 15 Jan 2024 11:25:24 +0800
> > > From: Yuan Yao
> > > Subject: Re: [PATCH v7 08/16] i386: Expose
On Thu, Jan 11, 2024 at 01:20:17PM -0500, Nick Briggs wrote:
> Solaris has #defines for htonll and ntohll which cause syntax errors
> when compiling code that attempts to (re)define these functions..
>
> Signed-off-by: Nick Briggs
I left the other QGA patch for QGA maintainers, assuming this
At present we expect struct arm_boot_info::get_dtb() to return the
device tree pointer as well as the device tree size. However, this
is not necessary as we can get the device tree size via the device
tree header directly. Change get_dtb() signature to drop the *size
argument, and get the size by
The Arm dtb changes caused an address change:
DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x0001)
{
[ ... ]
-Name (MEMA, 0x43C8)
+Name (MEMA, 0x43D8)
}
Signed-off-by: Bin Meng
---
tests/data/acpi/virt/SSDT.memhp | Bin 1817 -> 1817 bytes
1 file changed, 0
By default, QEMU generates a 1 MiB sized device tree. This appears
to be unnecessary, as the actual size is much smaller than what the
DTB header claims. Let's pack it to save some room.
Bin Meng (3):
hw/arm: Refactor struct arm_boot_info::get_dtb()
hw/arm: Pack the QEMU generated device
By default QEMU generates a 1 MiB sized device tree. Let's pack it
to save some room.
Signed-off-by: Bin Meng
---
hw/arm/boot.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index ff1173299f..511ec10ed0 100644
--- a/hw/arm/boot.c
+++
On 1/15/2024 12:09 PM, Zhao Liu wrote:
Hi Yuan,
On Mon, Jan 15, 2024 at 11:25:24AM +0800, Yuan Yao wrote:
Date: Mon, 15 Jan 2024 11:25:24 +0800
From: Yuan Yao
Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
On Mon, Jan 08, 2024 at 04:27:19PM +0800, Zhao Liu wrote:
On 1/15/2024 11:48 AM, Zhao Liu wrote:
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:42:41PM +0800, Xiaoyao Li wrote:
Date: Sun, 14 Jan 2024 22:42:41 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
CPUID[0x801D].EAX[bits 25:14]
On 1/8/2024 4:27
On 1/15/2024 11:40 AM, Zhao Liu wrote:
+{
+uint32_t num_ids = 0;
+
+switch (share_level) {
+case CPU_TOPO_LEVEL_CORE:
+num_ids = 1 << apicid_core_offset(topo_info);
+break;
+case CPU_TOPO_LEVEL_DIE:
+num_ids = 1 << apicid_die_offset(topo_info);
+
On 1/15/2024 11:27 AM, Zhao Liu wrote:
On Sun, Jan 14, 2024 at 09:49:18PM +0800, Xiaoyao Li wrote:
Date: Sun, 14 Jan 2024 21:49:18 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhuocheng Ding
On Thu, Jan 11, 2024 at 10:58:49AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Wed, Jan 10, 2024 at 11:42:18AM -0300, Fabiano Rosas wrote:
> >> Peter Xu writes:
> >>
> >> > On Tue, Jan 09, 2024 at 11:46:32AM -0300, Fabiano Rosas wrote:
> >> >> Hm, it would be better to avoid the
Hi Xiaoyao,
On Mon, Jan 15, 2024 at 11:51:05AM +0800, Xiaoyao Li wrote:
> Date: Mon, 15 Jan 2024 11:51:05 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
> topo in CPUID[4]
>
> On 1/11/2024 4:43 PM, Zhao Liu wrote:
> > Hi Xiaoyao,
> >
> >
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> For better debuggability and observability.
>
> Signed-off-by: Si-Wei Liu
> ---
> net/trace-events | 1 +
> net/vhost-vdpa.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/net/trace-events b/net/trace-events
> index
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> For better debuggability and observability.
>
> Signed-off-by: Si-Wei Liu
> ---
> net/trace-events | 2 ++
> net/vhost-vdpa.c | 7 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/net/trace-events b/net/trace-events
> index
Hi Yuan,
On Mon, Jan 15, 2024 at 11:25:24AM +0800, Yuan Yao wrote:
> Date: Mon, 15 Jan 2024 11:25:24 +0800
> From: Yuan Yao
> Subject: Re: [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F]
>
> On Mon, Jan 08, 2024 at 04:27:19PM +0800, Zhao Liu wrote:
> > From: Zhao Liu
> >
> > Linux
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> For better debuggability and observability.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> For better debuggability and observability.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/trace-events | 2 +-
> hw/virtio/vhost-vdpa.c | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/virtio/trace-events
On 1/11/2024 4:43 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Wed, Jan 10, 2024 at 05:31:28PM +0800, Xiaoyao Li wrote:
Date: Wed, 10 Jan 2024 17:31:28 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
topo in CPUID[4]
On 1/8/2024 4:27 PM, Zhao Liu
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> For better debuggability and observability.
>
> Signed-off-by: Si-Wei Liu
> ---
> net/trace-events | 3 +++
> net/vhost-vdpa.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/net/trace-events b/net/trace-events
> index
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Fix an issue where cancellation of ongoing migration ends up
> with no network connectivity.
>
> When canceling migration, SVQ will be switched back to the
> passthrough mode, but the right call fd is not programed to
> the device and the svq's
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Should help live migration downtime on source host. Below are the
> coalesced dma_unmap time series on 2 queue pair config (no
> dedicated descriptor group ASID for SVQ).
It's better to explain how we can batch into a single call (e.g do we
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 08:42:00PM +0800, Xiaoyao Li wrote:
> Date: Sun, 14 Jan 2024 20:42:00 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 09/16] i386: Support module_id in X86CPUTopoIDs
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhuocheng Ding
> >
> > Add module_id
On Fri, Jan 12, 2024 at 10:40:28AM +, Daniel P. Berrangé wrote:
> On Fri, Jan 12, 2024 at 08:01:36AM +0800, Peter Xu wrote:
> > On Thu, Jan 11, 2024 at 03:46:02PM -0300, Fabiano Rosas wrote:
> > > > (1) Does this apply to all io channel users, or only migration?
> > >
> > > All file channel
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:42:41PM +0800, Xiaoyao Li wrote:
> Date: Sun, 14 Jan 2024 22:42:41 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 15/16] i386: Use offsets get NumSharingCache for
> CPUID[0x801D].EAX[bits 25:14]
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From:
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Introduce new API. No functional change on existing API.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Coalesce map or unmap operations to exact one DMA
> batch to reduce potential impact on performance.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Coalesce multiple map or unmap operations to just one
> so that all mapping setup or teardown can occur in a
> single DMA batch.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> So that the batching API can be called from other file
> externally than the local.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/vhost-vdpa.c | 21 +++--
> include/hw/virtio/vhost-vdpa.h | 3 +++
> 2 files changed,
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:31:50PM +0800, Xiaoyao Li wrote:
> Date: Sun, 14 Jan 2024 22:31:50 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode
> CPUID[4]
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhao Liu
> >
> >
On Mon, Jan 08, 2024 at 04:27:19PM +0800, Zhao Liu wrote:
> From: Zhao Liu
>
> Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
> erroneous smp_num_siblings on Intel Hybrid platforms") is able to
> handle platforms with Module level enumerated via CPUID.1F.
>
> Expose the
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Then it's possible to specify ASID when calling the DMA
> batching API. If the ASID to work on doesn't align with
> the ASID for ongoing transaction, the API will fail the
> request and return negative, and the transaction will
> remain intact
On Sun, Jan 14, 2024 at 09:49:18PM +0800, Xiaoyao Li wrote:
> Date: Sun, 14 Jan 2024 21:49:18 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU
>
> On 1/8/2024 4:27 PM, Zhao Liu wrote:
> > From: Zhuocheng Ding
> >
> > Introduce cluster-id other
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> So that DMA batching API can operate on other ASID than 0.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/trace-events | 4 ++--
> hw/virtio/vhost-vdpa.c | 14 --
> 2 files changed, 10 insertions(+), 8 deletions(-)
>
> diff
On Fri, Dec 8, 2023 at 2:52 AM Si-Wei Liu wrote:
>
> Refactoring only. No functional change.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/trace-events | 2 +-
> hw/virtio/vhost-vdpa.c | 30 ++
> 2 files changed, 19 insertions(+), 13 deletions(-)
>
> diff --git
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> No functional changes. Rename only.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/vhost-vdpa.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
> index
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> Refactoring only. No functional change.
>
> Signed-off-by: Si-Wei Liu
Acked-by: Jason Wang
Thanks
> ---
> hw/virtio/trace-events | 2 +-
> hw/virtio/vhost-vdpa.c | 25 -
> 2 files changed, 17 insertions(+), 10
On 1/15/24 13:08, guoguangyao wrote:
When closing PCREL, qemu-system-x86_64 run into error.
Eip modification here leads to the result. Using s->pc
in func gen_update_eip_next() solves the problem.
Fixes: b5e0d5d22fbf("target/i386: Fix 32-bit wrapping of pc/eip computation")
Signed-off-by:
On Mon, Jan 15, 2024 at 10:40 AM Jason Wang wrote:
>
> On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
> >
> > No functional changes. Rename only.
> >
> > Signed-off-by: Si-Wei Liu
> > ---
> > hw/virtio/vhost-vdpa.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff
Hi Xiaoyao,
On Sun, Jan 14, 2024 at 10:11:59PM +0800, Xiaoyao Li wrote:
> Date: Sun, 14 Jan 2024 22:11:59 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
> topo in CPUID[4]
>
> On 1/11/2024 4:43 PM, Zhao Liu wrote:
> > Hi Xiaoyao,
> >
> >
On Fri, Dec 8, 2023 at 2:51 AM Si-Wei Liu wrote:
>
> No functional changes. Rename only.
>
> Signed-off-by: Si-Wei Liu
> ---
> hw/virtio/vhost-vdpa.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
> index
On Tue, Jan 2, 2024 at 11:29 AM Jason Wang wrote:
>
> When HASH_REPORT is negotiated, the guest_hdr_len might be larger than
> the size of the mergeable rx buffer header. Using
> virtio_net_hdr_mrg_rxbuf during the header swap might lead a stack
> overflow in this case. Fixing this by using
On Fri, Jan 5, 2024 at 12:45 AM Stefan Hajnoczi wrote:
>
> On Thu, 4 Jan 2024 at 11:30, Daniel P. Berrangé wrote:
> >
> > We've previously bumped up the timeouts in the netdev-socket qtest
> > to supposedly fix non-deterministic failures, however, the failures
> > are still hitting CI.
> >
> > A
When closing PCREL, qemu-system-x86_64 run into error.
Eip modification here leads to the result. Using s->pc
in func gen_update_eip_next() solves the problem.
Fixes: b5e0d5d22fbf("target/i386: Fix 32-bit wrapping of pc/eip computation")
Signed-off-by: guoguangyao
modified:
On Sat, Jan 13, 2024 at 12:05 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This version is a resend of patches 10 to 17 from v4, reviewed-by and
> tested-by tags added, rebased with Alistair's riscv-to-apply.next.
> Patches 01 to 09 of v4 are already queued.
>
> All patches acked.
>
> Changes
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> -Original Message-
> From: Taylor Simpson
> Sent: Monday, January 8, 2024 4:49 PM
> To: qemu-devel@nongnu.org
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Sid Manning ; Marco
> Liebel (QUIC) ; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
On Fri, Jan 12, 2024 at 4:18 PM Wentao Jia wrote:
>
> Hi, Michael and Jason
>
> Do you have any other comments?
> Is there a schedule for merge the patch into the community?
> Thank you
I think as discussed, we need to add compatibility support for those features.
Thanks
>
> Wentao
>
>
On 1/13/24 11:22, Vineet Gupta wrote:
Now we just need to debug what in the vdso call frame information is
wrong and any pointers to debug that would be appreciated, even if you
are able to fix it right away ;-)
The only way is to step through uw_frame_state_for() in libgcc and figure out
This is intended to address a coverity finding: CID 1527408.
Signed-off-by: Brian Cain
---
target/hexagon/mmvec/decode_ext_mmvec.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/hexagon/mmvec/decode_ext_mmvec.c
b/target/hexagon/mmvec/decode_ext_mmvec.c
index
This update includes support for privileged instructions.
Signed-off-by: Brian Cain
---
tests/docker/dockerfiles/debian-hexagon-cross.docker | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker
On Tue, 9 Jan 2024, Daniel P. Berrangé wrote:
> On Thu, Nov 09, 2023 at 03:52:38PM +0300, Alexander Monakov wrote:
> > I'd like to ping this patch on behalf of Mikhail.
> >
> > https://patchew.org/QEMU/20231027143704.7060-1-mmroma...@ispras.ru/
> >
> > If this needs to be split up a bit to
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
From AMD's APM, NumSharingCache
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
On 1/11/2024 4:43 PM, Zhao Liu wrote:
Hi Xiaoyao,
On Wed, Jan 10, 2024 at 05:31:28PM +0800, Xiaoyao Li wrote:
Date: Wed, 10 Jan 2024 17:31:28 +0800
From: Xiaoyao Li
Subject: Re: [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache
topo in CPUID[4]
On 1/8/2024 4:27 PM, Zhao Liu
Am 14. Januar 2024 13:03:07 UTC schrieb "Michael S. Tsirkin" :
>On Sun, Jan 14, 2024 at 12:52:53PM +, Bernhard Beschow wrote:
>>
>>
>> Am 14. Januar 2024 12:39:00 UTC schrieb Bernhard Beschow :
>> >This series implements relocation of the SuperI/O functions of the VIA south
>> >
>>
Hi
On Fri, Jan 12, 2024 at 5:57 PM Fiona Ebner wrote:
>
> With VNC, it can be that a client sends a VNC_MSG_CLIENT_CUT_TEXT
> message before sending a VNC_MSG_CLIENT_SET_ENCODINGS message with
> VNC_ENCODING_CLIPBOARD_EXT for configuring the clipboard extension.
>
> This means that
On 1/8/2024 4:27 PM, Zhao Liu wrote:
From: Zhuocheng Ding
Introduce cluster-id other than module-id to be consistent with
CpuInstanceProperties.cluster-id, and this avoids the confusion
of parameter names when hotplugging.
I don't think reusing 'cluster' from arm for x86's 'module' is a good
On Sun, Jan 14, 2024 at 12:52:53PM +, Bernhard Beschow wrote:
>
>
> Am 14. Januar 2024 12:39:00 UTC schrieb Bernhard Beschow :
> >This series implements relocation of the SuperI/O functions of the VIA south
> >
> >bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t
> >
Am 14. Januar 2024 12:39:00 UTC schrieb Bernhard Beschow :
>This series implements relocation of the SuperI/O functions of the VIA south
>
>bridges which resolves some FIXME's. It is part of my via-apollo-pro-133t
>
>branch [1] which is an extension of bringing the VIA south bridges to the PC
>
ParallelState::portio_list isn't used inside ParallelState context but only
inside ISAParallelState context, so move it there.
Signed-off-by: Bernhard Beschow
Reviewed-by: BALATON Zoltan
---
include/hw/char/parallel-isa.h | 2 ++
include/hw/char/parallel.h | 2 --
hw/char/parallel.c
FDCtrl::iomem isn't used inside FDCtrl context but only inside FDCtrlSysBus
context, so move it there.
Signed-off-by: Bernhard Beschow
Reviewed-by: BALATON Zoltan
---
hw/block/fdc-internal.h | 2 --
hw/block/fdc-sysbus.c | 6 --
2 files changed, 4 insertions(+), 4 deletions(-)
diff
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