time before posting. But the impact of the
new helpers is huge, and AIUI Richard wants to get rid of GETPC_LDST
so here are these.
Reviewed-by: Alexander Graf ag...@suse.de
Alex
Paolo Bonzini (2):
tcg-ppc: fix qemu_ld/qemu_st for AIX ABI
tcg-ppc: use new return-argument ld/st helpers
On 05.09.2013, at 11:48, Alexey Kardashevskiy wrote:
On 09/05/2013 07:16 PM, Alexander Graf wrote:
On 05.09.2013, at 06:54, Alexey Kardashevskiy wrote:
On 09/05/2013 02:30 PM, David Gibson wrote:
[...]
#endif /* TARGET_PPC64 */
}
@@ -1082,6 +1102,9 @@ int
On 05.09.2013, at 12:16, Paul Mackerras wrote:
On Wed, Sep 04, 2013 at 04:32:20PM -0500, Anthony Liguori wrote:
On Wed, Sep 4, 2013 at 8:37 AM, Alexander Graf ag...@suse.de wrote:
So IMHO this whole thing should be orthogonal to -cpu.
Well, since we cannot change CPU class on the fly
On 05.09.2013, at 12:17, Alexey Kardashevskiy wrote:
On 09/05/2013 07:27 PM, Alexander Graf wrote:
On 05.09.2013, at 09:40, Alexey Kardashevskiy wrote:
On 09/05/2013 05:08 PM, Alexander Graf wrote:
Am 05.09.2013 um 07:58 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
On the real
On 01.08.2013, at 16:12, Jason J. Herne wrote:
From: Jason J. Herne jjhe...@us.ibm.com
Define new SCLP codes to improve code readability.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/sclp.c |2 +-
include/hw/s390x/sclp.h |8
2 files changed, 9
On 05.09.2013, at 14:04, Alexey Kardashevskiy wrote:
On 09/05/2013 08:21 PM, Alexander Graf wrote:
On 05.09.2013, at 12:17, Alexey Kardashevskiy wrote:
On 09/05/2013 07:27 PM, Alexander Graf wrote:
On 05.09.2013, at 09:40, Alexey Kardashevskiy wrote:
On 09/05/2013 05:08 PM
On 05.09.2013, at 13:44, Benjamin Herrenschmidt wrote:
On Thu, 2013-09-05 at 11:58 +0200, Alexander Graf wrote:
Yes. I do not really understand the problem here (and I am not
playing
dump). Do you suggest sending just the guest timebase and do not
send the
host timebase and the offset
On 01.08.2013, at 16:12, Jason J. Herne wrote:
From: Jason J. Herne jjhe...@us.ibm.com
Introduces global access to storage key data so we can set it for each cpu in
the S390 cpu initialization routine.
Signed-off-by: Jason J. Herne jjhe...@us.ibm.com
---
hw/s390x/s390-virtio-ccw.c |
On 01.08.2013, at 16:12, Jason J. Herne wrote:
From: Jason J. Herne jjhe...@us.ibm.com
Modify s390_cpu_addr2state to allow fetching state information for cpu
addresses
above smp_cpus. Hotplug requires this capability.
Also add s390_cpu_set_state function to allow modification of
On 01.08.2013, at 16:12, Jason J. Herne wrote:
From: Jason J. Herne jjhe...@us.ibm.com
s390_new_cpu is created to encapsulate the creation of a new QOM S390CPU
object given a cpuid and a model string.
All actual cpu initialization code is moved from boot time specific
/cpu/devices/cpuN/online
Hot unplugging is currently not implemented by this code.
Very simple and clean patch set. I don't think it deserves the RFC tag.
Apart from the minor comments I had consider it
Reviewed-by: Alexander Graf ag...@suse.de
Alex
On 05.09.2013, at 13:40, Benjamin Herrenschmidt wrote:
On Thu, 2013-09-05 at 11:08 +0200, Alexander Graf wrote:
On 04.09.2013, at 23:05, Richard Henderson wrote:
This lets us change le_mode to end_mode and fold away nearly all
of the tests for the current cpu endianness, and removing all
On 05.09.2013, at 13:55, Paul Mackerras wrote:
On Thu, Sep 05, 2013 at 12:19:09PM +0200, Alexander Graf wrote:
On 05.09.2013, at 12:16, Paul Mackerras wrote:
On Wed, Sep 04, 2013 at 04:32:20PM -0500, Anthony Liguori wrote:
On Wed, Sep 4, 2013 at 8:37 AM, Alexander Graf ag...@suse.de
On 05.09.2013, at 14:49, Alexey Kardashevskiy wrote:
On 09/05/2013 10:16 PM, Alexander Graf wrote:
On 05.09.2013, at 14:04, Alexey Kardashevskiy wrote:
On 09/05/2013 08:21 PM, Alexander Graf wrote:
On 05.09.2013, at 12:17, Alexey Kardashevskiy wrote:
On 09/05/2013 07:27 PM
On 05.09.2013, at 15:05, Andreas Färber wrote:
Am 05.09.2013 14:54, schrieb Alexander Graf:
On 01.08.2013, at 16:12, Jason J. Herne wrote:
From: Jason J. Herne jjhe...@us.ibm.com
Latest code for cpu Hotplug on S390 architecture. This one is vastly
simpler
than v2 as we have
Glibc when built for newer kernels assumes that the sendmmsg syscall is
available.
Without it, dns resolution simply fails to work.
Wrap the syscall with existing infrastructure so that we don't have a host
dependency
on sendmmsg.
Signed-off-by: Alexander Graf ag...@suse.de
---
linux-user
On 05.09.2013, at 15:36, Benjamin Herrenschmidt wrote:
On Thu, 2013-09-05 at 14:37 +0200, Alexander Graf wrote:
Hrm, I think I'm starting to understand what this is about. So what we want
is
- timebase in guest
- timebase frequency in guest
- wall clock time in host
That way
On 05.09.2013, at 16:26, Benjamin Herrenschmidt wrote:
On Thu, 2013-09-05 at 16:14 +0200, Andreas Färber wrote:
Are you thinking of POWER8 having a different frequency than POWER8 in
compat mode? Because migration from one -cpu to another is not supported
elsewhere.
Even if we want to
On 05.09.2013, at 18:01, Paolo Bonzini wrote:
Il 03/09/2013 10:17, Michael S. Tsirkin ha scritto:
On PPC64 systems MSI Messages are translated to system IRQ in a PCI
host bridge. This is already supported for emulated MSI/MSIX but
not for irqfd where the current QEMU allocates IRQ numbers
Am 06.09.2013 um 07:04 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
On 09/06/2013 12:24 AM, Alexey Kardashevskiy wrote:
On 09/05/2013 11:08 PM, Alexander Graf wrote:
On 05.09.2013, at 14:49, Alexey Kardashevskiy wrote:
On 09/05/2013 10:16 PM, Alexander Graf wrote:
On 05.09.2013
On 06.09.2013, at 10:10, Alexey Kardashevskiy wrote:
On the real hardware, RTAS is called in real mode and therefore
ignores top 4 bits of the address passed in the call.
This fixes QEMU to use softmmu which can chop top 4 bits
if MSR DR is not set.
Signed-off-by: Alexey Kardashevskiy
Am 09.09.2013 um 04:40 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
On 09/06/2013 01:11 AM, Alexander Graf wrote:
On 05.09.2013, at 16:26, Benjamin Herrenschmidt wrote:
On Thu, 2013-09-05 at 16:14 +0200, Andreas Färber wrote:
Are you thinking of POWER8 having a different frequency
Am 09.09.2013 um 07:58 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
On 09/09/2013 03:50 PM, Alexander Graf wrote:
Am 09.09.2013 um 04:40 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
On 09/06/2013 01:11 AM, Alexander Graf wrote:
On 05.09.2013, at 16:26, Benjamin Herrenschmidt wrote
On 09.09.2013, at 11:29, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-09 at 08:06 +0200, Alexander Graf wrote:
I think it's ok to restrict live migration to machines with the same
tb frequency when kvm is enabled. Whether you implement it through a
hardcoded 512Mhz or through a timebase
On 09.09.2013, at 11:38, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-09 at 11:32 +0200, Alexander Graf wrote:
On 09.09.2013, at 11:29, Benjamin Herrenschmidt wrote:
On Mon, 2013-09-09 at 08:06 +0200, Alexander Graf wrote:
I think it's ok to restrict live migration to machines
.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Acked-by: Alexander Graf ag...@suse.de
Peter C, will you take this into your tree?
Alex
; Sethi Varun-B16395; Bhushan Bharat-R65777; 'Peter
Maydell'; 'Santosh Shukla'; 'Alexander Graf'; 'Antonios Motakis';
'Christoffer
Dall'; 'kim.phill...@linaro.org'; kvm...@lists.cs.columbia.edu; kvm-
p...@vger.kernel.org; qemu-devel@nongnu.org
Subject: Re: vfio for platform devices - 9/5/2012
On 12.09.2013, at 16:45, Scott Wood wrote:
On Thu, 2013-09-12 at 16:23 -0500, Alexander Graf wrote:
On 12.09.2013, at 13:10, Scott Wood wrote:
On Thu, 2013-09-12 at 04:18 -0500, Bhushan Bharat-R65777 wrote:
and device disabling is not a standard like PCI. Do you think that we
might need
On 13.09.2013, at 00:20, David Gibson wrote:
On Mon, Sep 09, 2013 at 08:06:53AM +0200, Alexander Graf wrote:
Am 09.09.2013 um 07:58 schrieb Alexey Kardashevskiy a...@ozlabs.ru:
On 09/09/2013 03:50 PM, Alexander Graf wrote:
Am 09.09.2013 um 04:40 schrieb Alexey Kardashevskiy
Am 16.09.2013 um 07:15 schrieb Benoît Canet benoit.ca...@irqsave.net:
Hello,
I know a cloud provider worried about the fact that the /proc/cpuinfo of his
guests give a bogus frequency to his customer.
QEMU and the guests kernel currently have no way to reflect the host frequency
Am 16.09.2013 um 09:29 schrieb Jason J. Herne jjhe...@linux.vnet.ibm.com:
On 09/16/2013 09:53 AM, Christian Borntraeger wrote:
On 05/09/13 13:25, Alexander Graf wrote:
On 01.08.2013, at 16:12, Jason J. Herne wrote:
From: Jason J. Herne jjhe...@us.ibm.com
Define new SCLP codes
On 18.09.2013, at 05:19, Christian Borntraeger wrote:
From: Heinz Graalfs graa...@linux.vnet.ibm.com
This patch adds the necessary life migration pieces to the sclp code
by using vmstate_register.
Signed-off-by: Heinz Graalfs graa...@linux.vnet.ibm.com
Signed-off-by: Christian
On 18.09.2013, at 05:19, Christian Borntraeger wrote:
From: Heinz Graalfs graa...@linux.vnet.ibm.com
This patch adds the necessary life migration pieces to sclpquiesce
by using the vmstate_register.
Signed-off-by: Heinz Graalfs graa...@linux.vnet.ibm.com
Signed-off-by: Christian
(c) 2011 Alexander Graf
+ * Copyright IBM, Corp. 2013
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or (at
your
+ * option) any later version. See the COPYING file in the top-level
directory.
+ *
+ */
+
+#ifndef EBCDIC_H_
+#define EBCDIC_H_
+
+#ifndef
On 18.09.2013, at 05:19, Christian Borntraeger wrote:
From: Heinz Graalfs graa...@linux.vnet.ibm.com
Add simple support for SCLP line-mode also known as operating
system messages. This can be added in addition to or instead of
the SCLP full screen console with -device sclplmconsole.
On 18.09.2013, at 05:19, Christian Borntraeger wrote:
Alex,
here is a bunch of fixes/changes for sclp/eventfacility followed by a
move of the ebcdic conversion into a stand-alone header file and the
sclp line mode console.
Reviewed-by: Alexander Graf ag...@suse.de
Alex
Am 22.09.2013 um 13:47 schrieb Liu Ping Fan qemul...@gmail.com:
This is useful when pci assignment happens on sPAPR.
This patch doesn't sound useful on its own to me, thus probably belongs in a
greater patch set.
And without even a clear commit message that explains why exactly this is going
In order to support these 2 use cases, let's just create a fake color map
that covers exactly our normal true color 8 bit color space. That way we don't
lose anything over a client that wants true color.
Reported-by: Sascha Wehnert swehn...@suse.com
Signed-off-by: Alexander Graf ag...@suse.de
---
ui
On 25.09.2013, at 09:41, Anton Blanchard wrote:
From: Tom Musta tommu...@gmail.com
The CFAR, DAR and DSISR registers are currently missing from the
dictionary of registers that may be printed in the QEMU console.
These are interesting registers when debugging. With this patch,
the
On 25.09.2013, at 09:42, Anton Blanchard wrote:
From: Tom Musta tommu...@gmail.com
The Load Vector Element (lve*x) and Store Vector Element (stve*x)
instructions not only byte-swap in Little Endian mode, they also
invert the element that is accessed. For example, the RTL for
lvehx
On 25.09.2013, at 09:40, Anton Blanchard wrote:
From: Benjamin Herrenschmidt b...@kernel.crashing.org
Try loading the kernel as little endian if it fails big endian.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Reviewed-by: Anton Blanchard an...@samba.org
Thanks,
On 06.09.2013, at 14:54, Julio Guerra wrote:
2013/6/30 Alexander Graf ag...@suse.de:
The L2CR register contains a number of bits that either impose configuration
which we can't deal with or mean something is in progress until the bit is
0 again.
Since we don't model the former and we do
-by: Alexander Graf ag...@suse.de
Tested-by: Julio Guerra gu...@julio.in
---
target-ppc/translate_init.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d2645ba..fd45093 100644
On 24.09.2013, at 16:52, Tom Musta wrote:
This patch sequence provides the first release of support for the
Vector Scalar Extension (VSX) instructions that were introduced
in PowerISA V2.06.
Initially, three instructions are supported (lxvd2x, stxvd2x and
xxpermdi) -- these are required
On 24.09.2013, at 12:05, mike wrote:
On 09/24/2013 01:59 PM, Alexey Kardashevskiy wrote:
At the moment the size of the buffer is set to 64K which is
enough for approximately 150 VCPUs which is not the limit.
This increases the buffer up to 256K which allows having
a tree for approximately
On 24.09.2013, at 07:59, Alexey Kardashevskiy wrote:
At the moment the size of the buffer is set to 64K which is
enough for approximately 150 VCPUs which is not the limit.
This increases the buffer up to 256K which allows having
a tree for approximately 600 VCPUs which is way beyond the
/borntraeger/qemu.git tags/s390-next-20130924
for you to fetch changes up to 6a444f8507514b3707c8807ed11c176d3fbc5860:
s390/sclplmconsole: Add support for SCLP line-mode console (2013-09-20
13:55:30 +0200)
Acked-by: Alexander Graf ag...@suse.de
Alex
On 26.09.2013, at 08:37, Michael Ellerman wrote:
Some powerpc systems have support for a hardware random number generator
(hwrng). If such a hwrng is present the host kernel can provide access
to it via the H_RANDOM hcall.
The kernel advertises the presence of a hwrng with the
We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/Makefile.objs | 2 +-
target-arm/helper-a64.c | 26
This patch adds emulation support for the orr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 28 +++
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 120 +
3 files changed, 149
The VFP cmp and cmpe helpers are quite cryptic to understand. This is
mostly thanks to the fact that they hardcode values rather than use
their symbolic counterparts.
Make them use names instead.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper.c | 50
confused by accident.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/cpu.h| 5 +
target-arm/helper.c | 8
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ce835ef..e69bb74 100644
--- a/target-arm/cpu.h
+++ b/target-arm
When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.
Signed-off-by: Alexander Graf ag...@suse.de
This patch adds emulation support for SIMD ORR instructions (and, or, xor).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 66 ++
1 file changed, 66 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm
When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/cpu64.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
This adds handling for the b and bl instructions.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 61 ++
1 file changed, 61 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 73ccade
as in
the AArch64 instruction emulator. But this series is already quite
big, so let's get this one through first.
If you need a rootfs to try this out on, I recommend using our openSUSE
12.3 tarball:
http://download.opensuse.org/repositories/devel:/ARM:/AArch64:/12.3/images/
Alex
Alexander
This patch adds support for branch instructions that act on registers
rather than immediates (jmp, call, ret).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/target-arm/translate-a64.c
.
Signed-off-by: Alexander Graf ag...@suse.de
---
disas.c | 6 +-
disas/Makefile.objs | 1 +
disas/aarch64.c | 31 +++
include/disas/bfd.h | 1 +
4 files changed, 38 insertions(+), 1 deletion(-)
create mode 100644 disas/aarch64.c
diff --git a/disas.c b
This patch adds emulation for load and store instructions with register
offset.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b
This patch adds support for add and friends.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 85 +
target-arm/helper-a64.h| 3 +
target-arm/translate-a64.c | 150 +
3 files changed, 238
This patch adds decoding for the AdvSIMD scalar three same group with U == 0.
While at it, it also adds support for the ADD / SUB operations in this group.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 53 ++
1 file
This patch adds emulation support for the add immediate instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate
This patch adds emulation for the DUP instruction flavor that copies
GPR contents into vector register parts.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/target-arm
This patch adds emulation support for the SIMD shl instruction. It belongs
to the same instruction group as ushll and can probably be handled in a shared
function with that one eventually.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 50
This patch adds emulation for the INS instruction flavor that copies
GPR contents into vector register parts.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/target-arm
This patch adds support for the STP instruction. It spans pretty much
all store possibilities, so the patch also adds handling for load/store
of integer as well as vector registers.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 263
This patch adds emulation support for the extr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 63eca24
With AArch64 VFP can now handle 64bit wide VFP float-int conversions.
Add handlers for them.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper.c | 40 +---
target-arm/helper.h | 8
2 files changed, 33 insertions(+), 15 deletions
This patch adds emulation support for the ushll instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 52 ++
1 file changed, 52 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
We currently dulplicate load/store logic for simd operations throughout
the place. Fortunately they follow a pretty clear pattern, so let's
create common code to handle them.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 99
This patch adds emulation support for the adr instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 24
1 file changed, 24 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bc91324..00eda0f
This patch adds handling for barrier instructions as noops.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cbfc449..cfad24f 100644
--- a/target-arm
This patch adds emulation support for the orr immediate instruction
family with all its implementations (and, or, xor).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 96 +-
1 file changed, 95 insertions(+), 1 deletion
This patch adds emulation for the mrs instruction. It is very incomplete
though and will need major rework to become as dynamic and good as the
cp15 handling.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 33 +
1 file changed, 33
This patch adds emulation for the tbz/tbnz instructions.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 40
1 file changed, 40 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 2c2adb8
This patch adds emulation for the umov instruction that copies vector
register contents into GPRs.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/target-arm/translate
This patch adds emulation for the msr instruction. It suffers from the same
shortcomings as mrs emulation and should be combined with it.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 27 +++
1 file changed, 27 insertions(+)
diff --git
This patch adds emulation for the Floating-point data-processing (2 source)
group of instructions in their 32 bit flavors.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 57 ++
1 file changed, 57 insertions(+)
diff --git
The VFP cmp operations do a comparison and then store the result
in FPSCR.
For AArch64, we need to compare but store the result in normal PSTATE
instead. So split the comparison from FPSCR modifications.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper.c| 14
This patch adds emulation for the syscall (svc) instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 13 +
target-arm/translate.c | 5 -
target-arm/translate.h | 5 +
3 files changed, 18 insertions(+), 5 deletions(-)
diff --git
This patch adds emulation for the Floating-point data-processing (3 source)
group of instructions in their 64 bit flavors.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 46 ++
1 file changed, 46 insertions(+)
diff --git
This patch adds emulation for the movi instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 45 +
1 file changed, 45 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index c5d0def
This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 41 +
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 28
3
This patch adds handling for the sys instruction as noop.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index cfad24f..2c2adb8 100644
--- a/target
This patch adds support for the SIMD load/store multiple (post-indexed)
category of instructions.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 91 ++
1 file changed, 91 insertions(+)
diff --git a/target-arm/translate
This patch adds emulation for the conditional increment (cinc) instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 34 ++
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 17 +
3 files changed
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 36
1 file changed, 36 insertions(+)
diff --git a/target-arm/translate-a64.c b
This patch adds emulation support for variable (register based) shift
instructions such as ASRV, LSLV, LSRV, RORV.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 20
1 file changed, 20 insertions(+)
diff --git a/target-arm/translate-a64.c b
This patch adds support for the ADD (vector) instruction which is part
of the AdvSIMD scalar three same group.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/target-arm/translate
This patch adds support for the AdvSIMD modified immediate group with
all its suboperations (movi, orr, fmov, mvni, bic).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 129 +
1 file changed, 129 insertions(+)
diff --git
This patch adds handling for HINT instructions as noops.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index a2d5942..cbfc449 100644
--- a/target-arm
This patch adds emulation support for BFM and friends (SBFM, UBFM).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 9 +
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 86 +-
3 files changed, 95
The Add/subtract (with carry) instructions can also be handled by our
generic add instruction decoder, so get them handled by that one too.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/translate-a64.c
This patch adds emulation for the instruction group labeled
Floating-point - fixed-point conversions in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 22
This patch adds emulation support for various versions of ldr and str
instructions.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 124 +
1 file changed, 124 insertions(+)
diff --git a/target-arm/translate-a64.c b/target
This patch adds emulation for compare and branch instructions (cbz, cbnz)
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/translate-a64.c | 44
1 file changed, 44 insertions(+)
diff --git a/target-arm/translate-a64.c b/target-arm/translate
This patch adds emlulation support for the clz instruction.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 5 +
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 31 +++
3 files changed, 37 insertions(+)
diff --git
This patch adds emulation for most of the Data-processing (3 source) family
of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH, UMADDL, UMSUBL,
UMULH.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 14
target-arm/helper-a64.h| 2 ++
target-arm
This patch adds emlulation support for rev and rbit instructions.
Signed-off-by: Alexander Graf ag...@suse.de
---
target-arm/helper-a64.c| 19 +++
target-arm/helper-a64.h| 1 +
target-arm/translate-a64.c | 38 ++
3 files changed, 58
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