Re: [PATCH v7 16/16] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion

qdict_put_obj(qdict_out, profile->name, value); > +} > +} > + > static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, > const QDict *qdict_in, > Error **errp) > @@ -220,6 +233,7 @@ CpuModelExpansionInfo > *qmp_query_cpu_model_expansion(CpuModelExpansionType type, > riscv_obj_add_multiext_props(obj, qdict_out, > riscv_cpu_experimental_exts); > riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); > riscv_obj_add_named_feats_qdict(obj, qdict_out); > +riscv_obj_add_profiles_qdict(obj, qdict_out); > > /* Add our CPU boolean options too */ > riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); > -- > 2.41.0 > Reviewed-by: Andrew Jones

Re: [PATCH v7 02/16] target/riscv/tcg: do not use "!generic" CPU checks

, all others > won't. > > And now we can add a new, third CPU type, that will allow extensions to > be enabled and will not inherit defaults, without changing the existing > logic. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/tcg/tcg-cpu.c | 13 + > 1 file changed, 9 insertions(+), 4 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU

uot; CPU type first. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 30 +----- > 2 files changed, 22 insertions(+), 9 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH v7 03/16] target/riscv: add rv64i CPU

On Wed, Nov 01, 2023 at 06:27:02AM -0300, Daniel Henrique Barboza wrote: > > > On 11/1/23 06:02, Andrew Jones wrote: > > On Tue, Oct 31, 2023 at 05:39:03PM -0300, Daniel Henrique Barboza wrote: > > > We don't have any form of a 'bare bones' CPU. rv64, our

Re: [PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp()

On Wed, Nov 01, 2023 at 05:41:48PM -0300, Daniel Henrique Barboza wrote: > The setter() for the boolean attributes that set satp_mode (sv32, sv39, > sv48, sv57, sv64) considers that the CPU will always do a > set_satp_mode_max_supported() during cpu_init(). > > This is not the case for the KVM 'ho

Re: [PATCH v8 04/19] target/riscv/cpu.c: set satp_mode_max MBARE during satp_finalize()

On Wed, Nov 01, 2023 at 05:41:49PM -0300, Daniel Henrique Barboza wrote: > KVM CPUs can handle "cpu->cfg.satp_mode.supported == 0" because KVM will > make it do internally, not requiring the current SATP support from TCG. > > But other TCG CPUs doesn't deal well with it. We'll assert out before >

Re: [PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions

On Wed, Nov 01, 2023 at 05:41:50PM -0300, Daniel Henrique Barboza wrote: > We'll add a new bare CPU type that won't have any default priv_ver. This > means that the CPU will default to priv_ver = 0, i.e. 1.10.0. > > At the same we'll allow these CPUs to enable extensions at will, but > then, if th

Re: [PATCH v8 06/19] target/riscv: add rv64i CPU

V_CPU, > +.abstract = true, > +}, > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), > #if defined(TARGET_RISCV32) > @@ -1791,6 +1813,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), > +DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), > #endif > }; > > -- > 2.41.0 > We'll probably need to bring back the satp supported mode setting, as suggested on a previous patch, but otherwise Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp()

On Thu, Nov 02, 2023 at 09:53:50AM -0300, Daniel Henrique Barboza wrote: > > > On 11/2/23 06:24, Andrew Jones wrote: > > On Wed, Nov 01, 2023 at 05:41:48PM -0300, Daniel Henrique Barboza wrote: > > > The setter() for the boolean attributes that set satp_mode (sv32, sv39

Re: [PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions

On Thu, Nov 02, 2023 at 10:42:25AM -0300, Daniel Henrique Barboza wrote: > > > On 11/2/23 06:47, Andrew Jones wrote: > > On Wed, Nov 01, 2023 at 05:41:50PM -0300, Daniel Henrique Barboza wrote: > > > We'll add a new bare CPU type that won't have any default p

Re: [PATCH v9 03/19] target/riscv/tcg: update priv_ver on user_set extensions

* will take precedence over this priv_ver bump. > + */ The above comment would be better in cpu_validate_multi_ext_priv_ver() at the line where the bumping is done. > +cpu_validate_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); > +} > + > isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); > } > > -- > 2.41.0 > Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v9 04/19] target/riscv: add rv64i CPU

> > # cat /proc/device-tree/cpus/cpu@0/riscv,isa > rv64imafdc_zicntr_zicsr_zifencei_zihpm_zca_zcd# > > [1] https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones > --- > target/riscv/

Re: [PATCH v9 10/19] target/riscv/tcg: add user flag for profile support

On Thu, Nov 02, 2023 at 07:44:36PM -0300, Daniel Henrique Barboza wrote: ... > +if (profile->enabled) { > +/* > + * Note: the 'priv_spec' command line option, if present, > + * will take precedence over this priv_ver bump. > + */ > +

Re: [PATCH v9 18/19] target/riscv: add 'rva22u64' CPU

"bool", > cpu_get_profile, cpu_set_profile, > NULL, (void *)profile); > + > +/* > + * CPUs might enable a profile right from the start. > + * Enable its mandatory extensions right away in this > + * case. > + */ > +if (profile->enabled) { > +object_property_set_bool(cpu_obj, profile->name, true, NULL); > +} > } > } > > -- > 2.41.0 > Other than the naming nits. Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v9 19/19] target/riscv/tcg: do not support profiles for 'max' CPU

On Thu, Nov 02, 2023 at 07:44:45PM -0300, Daniel Henrique Barboza wrote: > There's no gain in allowing the 'max' CPU to support profiles, since it > already contains everything that QEMU can support. And we'll open the > door for 'unorthodox' stuff like users disabling profiles of the 'max' > CPU.

Re: [RFC PATCH 3/3] softmmu/vl: Add qemu_cpu_opts QemuOptsList

On Fri, Aug 25, 2023 at 08:16:51PM +0800, LIU Zhiwei wrote: > This make the cpu works the similar way like the -device option. > > For device option, > """ > ./qemu-system-riscv64 -device e1000,help > e1000 options: > acpi-index=- (default: 0) > addr= - Slot and optional functio

Re: [PATCH v2 1/2] hw/riscv/virt.c: fix non-KVM --enable-debug build

kvm_aia(s)) { > kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, > VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, > memmap[VIRT_APLIC_S].base, > -- > 2.41.0 > > I think I'd prefer /* We need this inlined for debug (-O0) builds */ static inline QEMU_ALWAYS_INLINE bool virt_use_kvm_aia(RISCVVirtState *s) { return kvm_enabled() && kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; } assuming that works. Either way, Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v2 2/2] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build

t; --- a/target/riscv/kvm_riscv.h > +++ b/target/riscv/kvm_riscv.h > @@ -26,5 +26,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t > group_shift, >uint64_t aia_irq_num, uint64_t aia_msi_num, > uint64_t aplic_base, uint64_t imsic_base, >uint64_t guest_num); > +void riscv_kvm_aplic_request(void *opaque, int irq, int level); > > #endif > -- > 2.41.0 > > I'd also try the always_inline trick with is_kvm_aia(), particularly because now we're inconsistent with how it's used. In two of the three places it's called we don't guard it with kvm_enabled(). But, I'm also mostly OK with this, so Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH 01/20] target/riscv: introduce TCG AccelCPUClass

t; +} > + > +static void tcg_cpu_class_init(CPUClass *cc) > +{ > +cc->init_accel_cpu = tcg_cpu_init_ops; > +} > + > +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) > +{ > +AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); > + > +acc->cpu_class_init = tcg_cpu_class_init; > +} > + > +static const TypeInfo tcg_cpu_accel_type_info = { > +.name = ACCEL_CPU_NAME("tcg"), > + > +.parent = TYPE_ACCEL_CPU, > +.class_init = tcg_cpu_accel_class_init, > +.abstract = true, > +}; need blank line here > +static void tcg_cpu_accel_register_types(void) > +{ > +type_register_static(&tcg_cpu_accel_type_info); > +} > +type_init(tcg_cpu_accel_register_types); > -- > 2.41.0 > > Appears to be consistent with target/i386/tcg/tcg-cpu.c, so Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH 02/20] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn()

gt; + > +riscv_cpu_validate_priv_spec(cpu, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return false; > +} > + > + riscv_cpu_validate_misa_priv(env, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return false; > +} > + > +if (cpu->cfg.epmp && !cpu->cfg.pmp) { > +/* > + * Enhanced PMP should only be available > + * on harts with PMP support > + */ > +error_setg(errp, "Invalid configuration: EPMP requires PMP support"); > +return false; > +} > + > +riscv_cpu_validate_set_extensions(cpu, &local_err); > +if (local_err != NULL) { > +error_propagate(errp, local_err); > +return false; > +} > + > +#ifndef CONFIG_USER_ONLY > +CPU(cs)->tcg_cflags |= CF_PCREL; > + > +if (cpu->cfg.ext_sstc) { > +riscv_timer_init(cpu); > +} > + > +if (cpu->cfg.pmu_num) { > +if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) > { > +cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, > + riscv_pmu_timer_cb, cpu); > +} > + } > +#endif > + > +return true; > +} > + > static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) > { > /* > @@ -41,6 +172,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void > *data) > AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); > > acc->cpu_class_init = tcg_cpu_class_init; > +acc->cpu_realizefn = tcg_cpu_realizefn; > } > > static const TypeInfo tcg_cpu_accel_type_info = { > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH 03/20] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c

+if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); > +} > +if (riscv_has_ext(env, RVD)) { > + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); > +} > +} > + > +if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { > +error_setg(errp, "Zcf extension is only relevant to RV32"); > +return; > +} > + > +if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { > +error_setg(errp, "Zcf extension requires F extension"); > +return; > +} > + > +if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { > +error_setg(errp, "Zcd extension requires D extension"); > +return; > +} > + > +if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || > + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { > +error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " > + "extension"); > +return; > +} > + > +if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { > +error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " > + "Zcd extension"); > +return; > +} > + > +if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { > +error_setg(errp, "Zcmt extension requires Zicsr extension"); > +return; > +} > + > +/* > + * In principle Zve*x would also suffice here, were they supported > + * in qemu > + */ > +if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || > + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh) && > +!cpu->cfg.ext_zve32f) { > +error_setg(errp, > + "Vector crypto extensions require V or Zve* extensions"); > +return; > +} > + > +if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) { > +error_setg( > +errp, > +"Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions"); > +return; > +} > + > +if (cpu->cfg.ext_zk) { > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); > +} > + > +if (cpu->cfg.ext_zkn) { > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); > +} > + > +if (cpu->cfg.ext_zks) { > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); > +} > + > +/* > + * Disable isa extensions based on priv spec after we > + * validated and set everything we need. > + */ > +riscv_cpu_disable_priv_spec_isa_exts(cpu); > +} > + > /* > * We'll get here via the following path: > * > diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h > new file mode 100644 > index 00..4cf35a8015 > --- /dev/null > +++ b/target/riscv/tcg/tcg-cpu.h > @@ -0,0 +1,28 @@ > +/* > + * riscv TCG cpu class initialization > + * > + * Copyright (c) 2023 Ventana Micro Systems Inc. > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > <http://www.gnu.org/licenses/>. > + */ > + > +#ifndef RISCV_TCG_CPU_H > +#define RISCV_TCG_CPU_H > + > +#include "cpu.h" > + > +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); > + > +#endif > + > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 04/20] target/riscv: move riscv_tcg_ops to tcg-cpu.c

GCPUOps riscv_tcg_ops = { This can be static again. > +.initialize = riscv_translate_init, > +.synchronize_from_tb = riscv_cpu_synchronize_from_tb, > +.restore_state_to_opc = riscv_restore_state_to_opc, > + > +#ifndef CONFIG_USER_ONLY > +.tlb_fill = riscv_cpu_tlb_fill, >

Re: [PATCH 07/20] target/riscv/cpu.c: add .instance_post_init()

On Fri, Aug 25, 2023 at 10:08:40AM -0300, Daniel Henrique Barboza wrote: > All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU > calls riscv_init_max_cpu_extensions(). Both can be moved to a common > instance_post_init() callback, implemented in riscv_cpu_post_init(), > called by a

Re: [PATCH 08/20] target/riscv: move 'host' CPU declaration to kvm.c

riscv_kvm_cpu_class_init(ObjectClass *c, void *data) > +{ > +RISCVCPUClass *rcc = RISCV_CPU_CLASS(c); > + > +rcc->user_extension_properties = true; > +} > + > +static const TypeInfo riscv_kvm_cpu_type_infos[] = { > +{ > +.name = TYPE_RISCV_CPU_HOST, > +.parent = TYPE_RISCV_CPU, > +.instance_init = riscv_host_cpu_init, > +.class_init = riscv_kvm_cpu_class_init, > +} > +}; > + > +DEFINE_TYPES(riscv_kvm_cpu_type_infos) > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH 09/20] target/riscv/cpu.c: mark extensions arrays as 'const'

+const RISCVCPUMultiExtConfig *prop; > + > +for (prop = array; prop && prop->name; prop++) { > riscv_cpu_add_kvm_unavail_prop(obj, prop->name); > } > } > @@ -1659,7 +1663,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) > { > RISCVCPU *cpu = RISCV_CPU(obj); > CPURISCVState *env = &cpu->env; > -RISCVCPUMultiExtConfig *prop; > +const RISCVCPUMultiExtConfig *prop; > > /* Enable RVG, RVJ and RVV that are disabled by default */ > set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); > -- > 2.41.0 > > Other than the commit message change, Reviewed-by: Andrew Jones

Re: [PATCH 10/20] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c

v = DEVICE(obj); > + > +riscv_init_user_properties(obj); > +riscv_cpu_add_misa_properties(obj); > + > +riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > +riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); > +riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); > + > +for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { > +/* Check if KVM created the property already */ > +if (object_property_find(obj, prop->name)) { > +continue; > +} > +qdev_property_add_static(dev, prop); > +} > +} > + > static void riscv_host_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h > index 7d4b7c60e2..81e08b8359 100644 > --- a/target/riscv/kvm_riscv.h > +++ b/target/riscv/kvm_riscv.h > @@ -19,7 +19,7 @@ > #ifndef QEMU_KVM_RISCV_H > #define QEMU_KVM_RISCV_H > > -void kvm_riscv_init_user_properties(Object *cpu_obj); > +void kvm_riscv_cpu_add_kvm_properties(Object *obj); > void kvm_riscv_reset_vcpu(RISCVCPU *cpu); > void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); > void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH 11/20] target/riscv: introduce KVM AccelCPUClass

On Fri, Aug 25, 2023 at 10:08:44AM -0300, Daniel Henrique Barboza wrote: > Add a KVM accelerator class like we did with TCG. The difference is > that, at least for now, we won't be using a realize() implementation for > this accelerator. > > We'll start by assiging kvm_riscv_cpu_add_kvm_properties

Re: [PATCH 12/20] target/riscv: move KVM only files to kvm subdir

son.build > index f0486183fa..c53962215f 100644 > --- a/target/riscv/meson.build > +++ b/target/riscv/meson.build > @@ -24,7 +24,6 @@ riscv_ss.add(files( >'zce_helper.c', >'vcrypto_helper.c' > )) > -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: > files('kvm-stub.c')) > > riscv_system_ss = ss.source_set() > riscv_system_ss.add(files( > @@ -39,6 +38,7 @@ riscv_system_ss.add(files( > )) > > subdir('tcg') > +subdir('kvm') > > target_arch += {'riscv': riscv_ss} > target_softmmu_arch += {'riscv': riscv_system_ss} > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH 13/20] target/riscv/kvm: refactor kvm_riscv_init_user_properties()

prop_array(obj, riscv_cpu_vendor_exts); > +riscv_cpu_add_kvm_unavail_prop_array(obj, > riscv_cpu_experimental_exts); > +} > > for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { > /* Check if we have a specific KVM handler for the option */ > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH 14/20] target/riscv/kvm: do not use riscv_cpu_add_misa_properties()

riscv_get_regs_core(CPUState *cs) > @@ -1301,12 +1312,6 @@ static void kvm_cpu_instance_init(CPUState *cs) > > if (rcc->user_extension_properties) { > kvm_riscv_add_cpu_user_properties(obj); > - riscv_add_satp_mode_properties(obj); > -riscv_cpu_add_misa_properties(obj); > - > -riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > -riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); > -riscv_cpu_add_kvm_unavail_prop_array(obj, > riscv_cpu_experimental_exts); > } > > for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 15/20] target/riscv/tcg: introduce tcg_cpu_instance_init()

v, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); > + > +for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > +isa_ext_update_enabled(cpu, prop->offset, true); > +} > + > +/* set vector version */ > +env->vext_ver =

Re: [PATCH 16/20] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c

rties(Object *cpu_obj) > +{ > +int i; > + > +for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { > +RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; > +int bit = misa_cfg->misa_bit; > + > +misa_cfg->name = riscv_get_misa_ext_name(bit); > +misa_cfg->description = riscv_get_misa_ext_description(bit); > + > +object_property_add(cpu_obj, misa_cfg->name, "bool", > +cpu_get_misa_ext_cfg, > +cpu_set_misa_ext_cfg, > +NULL, (void *)misa_cfg); > +object_property_set_description(cpu_obj, misa_cfg->name, > +misa_cfg->description); > +object_property_set_bool(cpu_obj, misa_cfg->name, > + misa_cfg->enabled, NULL); > +} > +} > + > static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, >void *opaque, Error **errp) > { > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 17/20] target/riscv/cpu.c: export isa_edata_arr[]

h > index 4269523e24..d9a17df46a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig > riscv_cpu_vendor_exts[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > extern Property riscv_cpu_options[]; > > +typedef struct isa_ext_data { > +const char *name; > +int min_version; > +int ext_enable_offset; > +} RISCVIsaExtData; > +extern const RISCVIsaExtData isa_edata_arr[]; > + > void riscv_add_satp_mode_properties(Object *obj); > > /* CSR function table */ > -- > 2.41.0 > > Otherwise, Reviewed-by: Andrew Jones

Re: [PATCH 18/20] target/riscv/cpu: move priv spec functions to tcg-cpu.c

t;ext_enable_offset) && > +(env->priv_ver < edata->min_version)) { > + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); > +#ifndef CONFIG_USER_ONLY > +warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > +" because privilege spec version does not match", > +edata->name, env->mhartid); > +#else > +warn_report("disabling %s extension because " > +"privilege spec version does not match", > +edata->name); > +#endif > +} > +} > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly. > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH 19/20] target/riscv: add 'tcg_supported' class property

On Fri, Aug 25, 2023 at 10:08:52AM -0300, Daniel Henrique Barboza wrote: > This property indicates if a CPU supports TCG acceleration. All CPUs but > the 'host' CPU supports it. > > The error in tcg_cpu_realizefn() can now be made generic in case more > non-TCG CPUs are added in the future. > > S

Re: [PATCH 20/20] target/riscv: add 'kvm_supported' class property

On Fri, Aug 25, 2023 at 10:08:53AM -0300, Daniel Henrique Barboza wrote: > This follows the same idea of 'tcg_support' property added in the > previous patch. Note that we're now implementing the 'cpu_realizefn' for > the KVMAccel class since this verification is done in realize() time. > > Suppor

Re: [PATCH RESEND v8 01/20] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[]

listair Francis > --- > target/riscv/cpu.c | 33 +++-- > 1 file changed, 23 insertions(+), 10 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 02/20] target/riscv/cpu.c: skip 'bool' check when filtering KVM props

t;bool", > +NULL, cpu_set_cfg_unavailable, > +NULL, (void *)prop->name); > +continue; > } > #endif > qdev_property_add_static(dev, prop); > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 03/20] target/riscv/cpu.c: split kvm prop handling to its own helper

iewed-by: Alistair Francis > --- > target/riscv/cpu.c | 65 ++ > 1 file changed, 42 insertions(+), 23 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 04/20] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[]

ic void riscv_cpu_add_user_properties(Object *obj) > qdev_property_add_static(dev, prop); > } > > -for (int i = 0; i < ARRAY_SIZE(riscv_cpu_options); i++) { > -qdev_property_add_static(dev, &riscv_cpu_options[i]); > +for (prop = riscv_cpu_options; prop && prop->name; prop++) { > +qdev_property_add_static(dev, prop); > } > } > > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 05/20] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]

++) { > qdev_property_add_static(dev, prop); > } > + > +for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { > +qdev_property_add_static(dev, prop); > +} > } > > static Property riscv_cpu_properties[] = { > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 08/20] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array()

vail_prop(obj, prop->name); > -} > +riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); > +riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); > +riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); > > for (prop = riscv_cpu_options; prop && prop->name; prop++) { > /* Check if KVM created the property already */ > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 06/20] target/riscv/cpu.c: split vendor exts from riscv_cpu_extensions[]

avail_prop(obj, prop->name); > } > @@ -2017,6 +2024,10 @@ static void riscv_cpu_add_user_properties(Object *obj) > qdev_property_add_static(dev, prop); > } > > +for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) { > + qdev_property_add_static(dev, prop); > +} > + > for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 10/20] target/riscv: add 'max' CPU type

zkne_zknh_zkr_zks_zksed_zksh_zkt_zve32f_zve64f_zve64d_ > smstateen_sscofpmf_sstc_svadu_svinval_svnapot_svpbmt > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Weiwei Li > Reviewed-by: Alistair Francis > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 56 ++ > 2 files changed, 57 insertions(+) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 07/20] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array()

} > +riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_extensions); > +riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_options); > +riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_vendor_exts); > +riscv_cpu_add_qdev_prop_array(dev, riscv_cpu_experimental_exts); > } > > static Property riscv_cpu_properties[] = { > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 11/20] avocado, risc-v: add opensbi tests for 'max' CPU

On Thu, Aug 24, 2023 at 07:14:31PM -0300, Daniel Henrique Barboza wrote: > Add smoke tests to ensure that we'll not break the 'max' CPU type when > adding new ratified extensions to be enabled. I'm not really sure what this test proves other than we didn't remove the minimally supported set of ext

Re: [PATCH RESEND v8 12/20] target/riscv: deprecate the 'any' CPU type

2,6 +1522,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error > **errp) > RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); > Error *local_err = NULL; > > +if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) { > +warn_report("The 'any' CPU is deprecated and will be " > +"removed in the future."); > +} > + > cpu_exec_realizefn(cs, &local_err); > if (local_err != NULL) { > error_propagate(errp, local_err); > -- > 2.41.0 > > Besides the text edits, Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 13/20] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled

instead of > 'edata'. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 18 +- > 1 file changed, 9 insertions(+), 9 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 14/20] target/riscv: make CPUCFG() macro public

t; 3 files changed, 6 insertions(+), 6 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()

On Thu, Aug 24, 2023 at 07:14:35PM -0300, Daniel Henrique Barboza wrote: > During realize() time we're activating a lot of extensions based on some > criteria, e.g.: > > if (cpu->cfg.ext_zk) { > cpu->cfg.ext_zkn = true; > cpu->cfg.ext_zkr = true; > cpu->cfg.ext_zkt = tr

Re: [PATCH RESEND v8 16/20] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()

uot;cpu->cfg.ext_N = true|false". > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 50 +++------- > 1 file changed, 25 insertions(+), 25 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 17/20] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig

) calls that our macros are doing to populate > user properties. The macro was renamed to ADD_CPU_MULTIEXT_PROPS_ARRAY() > for clarity. Note that the non-extension properties in > riscv_cpu_options[] still need to be declared via qdev(). > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > --- > target/riscv/cpu.c | 257 - > 1 file changed, 158 insertions(+), 99 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 18/20] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions()

cmt", false, NULL); > +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); > +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); > +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); > > if (env->misa_mxl != MXL_RV32) { > -object_property_set_bool(obj, "zcf", false, NULL); > +isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); > } > } > > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 19/20] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update()

_is_user_set(ext_offset)) { > +return; > +} > + > if (value && env->priv_ver != PRIV_VERSION_LATEST) { > /* Do not enable it if priv_ver is older than min_version */ > min_version = cpu_cfg_ext_get_min_version(ext_offset); > -- > 2.41.0 > > Reviewed-by: Andrew Jones

Re: [PATCH RESEND v8 20/20] target/riscv/cpu.c: consider user option with RVG

On Thu, Aug 24, 2023 at 07:14:40PM -0300, Daniel Henrique Barboza wrote: > Enabling RVG will enable a set of extensions that we're not checking if > the user was okay enabling or not. And in this case we want to error > out, instead of ignoring, otherwise we will be inconsistent enabling RVG > with

Re: [PATCH RESEND v8 00/20] riscv: 'max' CPU, detect user choice in TCG

On Thu, Aug 24, 2023 at 07:14:20PM -0300, Daniel Henrique Barboza wrote: > Hi, > > This is a resend of these two patch sets because they no longer apply > into Alistair's riscv-to-apply.next: > > [PATCH v8 00/12] riscv: add 'max' CPU, deprecate 'any' > https://lore.kernel.org/qemu-riscv/202308152

Re: [PATCH v2 1/2] hw/riscv/virt.c: fix non-KVM --enable-debug build

On Thu, Aug 31, 2023 at 02:47:54PM +0200, Philippe Mathieu-Daudé wrote: > On 31/8/23 10:42, Andrew Jones wrote: > > On Wed, Aug 30, 2023 at 10:35:02AM -0300, Daniel Henrique Barboza wrote: > > > A build with --enable-debug and without KVM will fail as follows: > > >

Re: [PATCH] arm64: Restore trapless ptimer access

> > Quoting Andrew Jones: > > Simply reading the CNT register and writing back the same value is > enough to set an offset, since the timer will have certainly moved > past whatever value was read by the time it's written. QEMU > frequently saves and restores all registe

Re: [PATCH 20/20] target/riscv: add 'kvm_supported' class property

On Fri, Sep 01, 2023 at 05:57:46PM -0300, Daniel Henrique Barboza wrote: > > > On 8/31/23 09:47, Andrew Jones wrote: > > On Fri, Aug 25, 2023 at 10:08:53AM -0300, Daniel Henrique Barboza wrote: > > > This follows the same idea of 'tcg_support' property added

Re: [PATCH v9 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()

niel Henrique Barboza > --- > target/riscv/cpu.c | 43 ++++--- > 1 file changed, 40 insertions(+), 3 deletions(-) > Reviewed-by: Andrew Jones

Re: [PATCH v9 20/20] target/riscv/cpu.c: consider user option with RVG

t_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); > +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); > > env->misa_ext |= RVI | RVM | RVA | RVF | RVD; > env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; > -- > 2.41.0 > Reviewed-by: Andrew Jones

Re: [PATCH] arm64: Restore trapless ptimer access

402bd ("target-arm: kvm: Differentiate registers based on write-back levels") Thanks, drew > > Ciao, > > Claudio > > On 9/1/23 21:23, Colton Lewis wrote: > > On Fri, Sep 01, 2023 at 09:35:47AM +0200, Andrew Jones wrote: > >> On Thu, Aug 31, 2023 at 07:00:5

Re: [PATCH for-7.0] hw: Add compat machines for 7.0

On Fri, Dec 17, 2021 at 03:29:13PM +0100, Cornelia Huck wrote: > On Fri, Dec 17 2021, Daniel P. Berrangé wrote: > > > On Fri, Dec 17, 2021 at 09:13:55AM +0100, Cornelia Huck wrote: > >> On Wed, Dec 08 2021, Cornelia Huck wrote: > >> > >> > Add 7.0 machine types for arm/i440fx/q35/s390x/spapr. >

Re: [PATCH v2] hw: Add compat machines for 7.0

0) > + > static void virt_machine_6_2_options(MachineClass *mc) > { > +virt_machine_7_0_options(mc); > +compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); > } > -DEFINE_VIRT_MACHINE_AS_LATEST(6, 2) > +DEFINE_VIRT_MACHINE(6, 2) > > static void virt_machine_6_1_options(MachineClass *mc) > { For the arm parts Reviewed-by: Andrew Jones

Re: [PATCH v6 3/7] hw/acpi/aml-build: Improve scalability of PPTT generation

Thread */ > +(1 << 3), /* Node is a Leaf */ > +father_offset, uid++, NULL, 0); > +} > +} > + > +g_queue_free(list); > acpi_table_end(linker, &table); > } This patch actually increases the number of loops, since we need to visit higher hierarchical nodes twice (once to enqueue and once to dequeue). We do reduce code indentation and it looks like we could more easily skip hierarchy levels we don't want, though. While my impulse is to say we should just keep this simple and add another nested loop for clusters, I guess I'm OK with this too. Reviewed-by: Andrew Jones Thanks, drew

Re: [PATCH v6 1/7] hw/arm/virt: Support CPU cluster on ARM virt machine

es > +will be automatically computed: > + > +:: > + > +-smp 16,sockets=2,clusters=2,cores=2,threads=2,maxcpus=16 > + > Historically preference was given to the coarsest topology parameters > when computing missing values (ie sockets preferred over cores, which > were preferred over threads), however, this behaviour is considered > -- > 2.27.0 > Reviewed-by: Andrew Jones

Re: [PATCH v6 2/7] hw/arm/virt: Support cluster level in DT cpu-map

map_path = g_strdup_printf( > -"/cpus/cpu-map/socket%d/cluster0/core%d", > -cpu / ms->smp.cores, > +"/cpus/cpu-map/socket%d/cluster%d/core%d", > +cpu / (ms->smp.clusters * ms->smp.cores), > +(cpu / ms->smp.cores) % ms->smp.clusters, > cpu % ms->smp.cores); > } > qemu_fdt_add_path(ms->fdt, map_path); > -- > 2.27.0 > Reviewed-by: Andrew Jones

Re: [PATCH v6 4/7] hw/arm/virt-acpi-build: Make an ARM specific PPTT generator

On Mon, Jan 03, 2022 at 04:46:33PM +0800, Yanan Wang wrote: > We have a generic build_pptt() in hw/acpi/aml-build.c but it's > currently only used in ARM acpi initialization. Now we are going > to support the new CPU cluster parameter which is currently only > supported by ARM, it won't be a very g

Re: [PATCH v6 6/7] hw/arm/virt-acpi-build: Support cluster level in PPTT generation

(0 << 0), /* not a physical package */ > +father_offset, cluster, NULL, 0); > +} > +} > + > length = g_queue_get_length(list); > for (i = 0; i < length; i++) { > int core; > -- > 2.27.0 > Looks good except please do s/father_offset/parent_offset/ as I mentioned in an earlier patch. Reviewed-by: Andrew Jones

Re: [PATCH] hw/arm/virt: KVM: Enable PAuth when supported by the host

ses > it, it is possible to disable it by setting the 'pauth=off' CPU > property. > > Tested on an Apple M1 running 5.16-rc6. > > Cc: Eric Auger > Cc: Andrew Jones > Cc: Richard Henderson > Cc: Peter Maydell > Signed-off-by: Marc Zyngier > --- &g

Re: [Qemu-devel] [PATCH V7 0/2] Add option to configure guest vPMU

On Mon, Oct 24, 2016 at 11:39:59PM -0500, Wei Huang wrote: > >> V6->V7: > >> * change has_pmu variable type from OnOffAuto to Boolean > >> * only add "pmu" property to CPU under kvm mode, default ON > > > > Hmm, if we don't allow the property with TCG then switching a guest from > > KVM to TCG

Re: [Qemu-devel] [PATCH V7 0/2] Add option to configure guest vPMU

On Tue, Oct 25, 2016 at 11:55:05AM -0500, Wei Huang wrote: > > > On 10/25/2016 10:26 AM, Peter Maydell wrote: > > On 25 October 2016 at 08:33, Andrew Jones wrote: > >> On Mon, Oct 24, 2016 at 11:39:59PM -0500, Wei Huang wrote: > >>>>> V6->V7:

Re: [Qemu-devel] [PATCH V7 0/2] Add option to configure guest vPMU

On Tue, Oct 25, 2016 at 01:50:01PM -0500, Wei Huang wrote: > > > On 10/25/2016 12:56 PM, Andrew Jones wrote: > > >> > >> Compared with V7, my proposed solution above isn't so different as we > >> thought. Details below. In V7, > >> > &g

Re: [Qemu-devel] [PATCH V8 1/2] arm: Add an option to turn on/off vPMU support

| 2 +- > target-arm/cpu.c | 15 +++ > target-arm/cpu.h | 1 + > target-arm/cpu64.c | 2 ++ > target-arm/kvm64.c | 17 ++--- > 6 files changed, 34 insertions(+), 5 deletions(-) Reviewed-by: Andrew Jones > > dif

Re: [Qemu-devel] [PATCH V8 2/2] arm: virt: add PMU property to mach-virt machine type

. > This PMU option is not exposed to command line and is turned off in > virt-2.6 machine type. > > Reviewed-by: Andrew Jones > Signed-off-by: Wei Huang > --- > hw/arm/virt.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/arm/virt.c b/hw/arm/

Re: [Qemu-devel] when we add EL2 to QEMU TCG ARM emulation and the virt board, should it default on or off?

On Tue, Nov 01, 2016 at 05:16:59PM +, Peter Maydell wrote: > I'm working on turning on EL2 support in our TCG ARM emulation, > and one area I'm not sure about is whether it should default to > on or off. > > We have a few precedents: > > For EL3 support: > * the CPU property is enabled by de

Re: [Qemu-devel] [kvm-unit-tests PATCHv7 1/3] arm: Add PMU test

On Wed, Nov 02, 2016 at 05:22:15PM -0500, Wei Huang wrote: Missing From: Christopher Covington > Beginning with a simple sanity check of the control register, add > a unit test for the ARM Performance Monitors Unit (PMU). > > Signed-off-by: Christopher Covington Missing Signed-off-by: Wei

Re: [Qemu-devel] [kvm-unit-tests PATCHv7 2/3] arm: pmu: Check cycle count increases

On Wed, Nov 02, 2016 at 05:22:16PM -0500, Wei Huang wrote: Missing From: Christopher > Ensure that reads of the PMCCNTR_EL0 are monotonically increasing, > even for the smallest delta of two subsequent reads. > > Signed-off-by: Christopher Covington > Signed-off-by: Wei Huang > --- > arm/pmu.

Re: [Qemu-devel] [kvm-unit-tests PATCHv7 3/3] arm: pmu: Add CPI checking

From: Christopher s-o-b: Wei On Wed, Nov 02, 2016 at 05:22:17PM -0500, Wei Huang wrote: > Calculate the numbers of cycles per instruction (CPI) implied by ARM > PMU cycle counter values. > > Signed-off-by: Christopher Covington > --- > arm/pmu.c | 109 > +++

Re: [Qemu-devel] [kvm-unit-tests PATCHv7 0/3] ARM PMU tests

echo $SUBJECT | s/PATCHv7/PATCH v7/ (otherwise busts my filters) On Wed, Nov 02, 2016 at 05:22:14PM -0500, Wei Huang wrote: > Changes from v6: > * Add a new pmu testing for KVM mode in config file > * Add additional init code, including setting PMCNTENSET and PMCCFILTR, > before reading PMCCN

Re: [Qemu-devel] [kvm-unit-tests PATCHv7 1/3] arm: Add PMU test

On Thu, Nov 03, 2016 at 08:29:57AM -0600, c...@codeaurora.org wrote: > On 2016-11-03 04:14, Andrew Jones wrote: > > On Wed, Nov 02, 2016 at 05:22:15PM -0500, Wei Huang wrote: > > > > Missing > > From: Christopher Covington > > > > > > > Beg

Re: [Qemu-devel] [kvm-unit-tests PATCH v6 00/11] arm/arm64: add gic framework

Andre, Alex, Eric, anybody, Any more comments on this? If not, I'll send a pull request to Radim and Paolo to finally get this merged. Thanks, drew On Mon, Nov 14, 2016 at 10:08:28PM +0100, Andrew Jones wrote: > v6: > - rebased to latest master > - several other changes thank

Re: [Qemu-devel] [kvm-unit-tests PATCH v6 10/11] arm/arm64: gicv3: add an IPI test

On Wed, Nov 23, 2016 at 12:05:42PM +0100, Auger Eric wrote: > Hi Drew, > > On 14/11/2016 22:08, Andrew Jones wrote: > > Signed-off-by: Andrew Jones > > > > --- > > v6: move most gicv2/gicv3 wrappers to common code [Alex] > > v5: > > - fix copy+past

Re: [Qemu-devel] [kvm-unit-tests PATCH v6 11/11] arm/arm64: gic: don't just use zero

On Wed, Nov 23, 2016 at 12:28:34PM +0100, Auger Eric wrote: > Hi, > > On 14/11/2016 22:08, Andrew Jones wrote: > > Allow user to select who sends ipis and with which irq, > > rather than just always sending irq=0 from cpu0. > From a user point of view is there a way to kn

Re: [Qemu-devel] [kvm-unit-tests PATCH v6 11/11] arm/arm64: gic: don't just use zero

On Wed, Nov 23, 2016 at 02:33:31PM +0100, Auger Eric wrote: > > > On 23/11/2016 14:01, Andrew Jones wrote: > > On Wed, Nov 23, 2016 at 12:28:34PM +0100, Auger Eric wrote: > >> Hi, > >> > >> On 14/11/2016 22:08, Andrew Jones wrote: > >>>

Re: [Qemu-devel] [kvm-unit-tests PATCH v6 00/11] arm/arm64: add gic framework

On Wed, Nov 23, 2016 at 12:33:53PM +0100, Auger Eric wrote: > Hi, > On 23/11/2016 11:09, Alex Bennée wrote: > > > > Andrew Jones writes: > > > >> Andre, Alex, Eric, anybody, > >> > >> Any more comments on this? If not, I'll send a pull re

[Qemu-devel] [kvm-unit-tests PATCH v7 01/11] lib: xstr: allow multiple args

Make implementation equivalent to Linux's include/linux/stringify.h Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- lib/libcflat.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/libcflat.h b/lib/libcflat.h index c622198677c1..c3fa4f24c499 100644 ---

[Qemu-devel] [kvm-unit-tests PATCH v7 03/11] arm/arm64: smp: support more than 8 cpus

Reviewed-by: Andre Przywara Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v5: left cpus a u32 for now. Changing to u64 requires a change to devicetree. Will do it later. [Andre] v4: improved commit message --- arm/run | 19 --- arm/selftest.c

[Qemu-devel] [kvm-unit-tests PATCH v7 02/11] arm64: fix get_"sysreg32" and make MPIDR 64bit

mrs is always 64bit, so we should always use a 64bit register. Sometimes we'll only want to return the lower 32, but not for MPIDR, as that does define fields in the upper 32. Reviewed-by: Alex Bennée Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v5: switch arm32's ge

[Qemu-devel] [kvm-unit-tests PATCH v7 06/11] arm/arm64: add initial gicv2 support

Add some gicv2 support. This just adds init and enable functions, allowing unit tests to start messing with it. Reviewed-by: Andre Przywara Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v6: added comments (register offset headers) [Alex] v5: share/use only the modern register names

[Qemu-devel] [kvm-unit-tests PATCH v7 00/11] arm/arm64: add gic framework

iable sender and irq Available here: https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic-v7 Andrew Jones (10): lib: xstr: allow multiple args arm64: fix get_"sysreg32" and make MPIDR 64bit arm/arm64: smp: support more than 8 cpus arm/arm64: add some delay routines

[Qemu-devel] [kvm-unit-tests PATCH v7 07/11] arm/arm64: gicv2: add an IPI test

Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v6: move the spurious check to its own check_ function [drew] v5: use modern registers [Andre] v4: properly mask irqnr in ipi_handler v2: add more details in the output if a test fails, report spurious interrupts if we get them --- arm

[Qemu-devel] [kvm-unit-tests PATCH v7 09/11] arm/arm64: add initial gicv3 support

Reviewed-by: Alex Bennée Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v7: split lib/arm/gic.c into gic-v2/3.c [Eric] v6: - added comments [Alex] - added stride parameter to gicv3_set_redist_base [Andre] - redist-wait s/rwp/uwp/ and comment [Andre] - removed unnecessary wait-for

[Qemu-devel] [kvm-unit-tests PATCH v7 08/11] libcflat: add IS_ALIGNED() macro, and page sizes

From: Peter Xu These macros will be useful to do page alignment checks. Reviewed-by: Andre Przywara Reviewed-by: Eric Auger Signed-off-by: Peter Xu [drew: also added SZ_64K and changed to shifts] Signed-off-by: Andrew Jones --- v6: change to shifts [Alex] --- lib/libcflat.h | 6 ++ 1

[Qemu-devel] [kvm-unit-tests PATCH v7 11/11] arm/arm64: gic: don't just use zero

Allow user to select who sends ipis and with which irq, rather than just always sending irq=0 from cpu0. Signed-off-by: Andrew Jones --- v7: cleanup cmdline parsing and add complain on bad args [Eric] v6: - make sender/irq names more future-proof [drew] - sanity check inputs [drew

[Qemu-devel] [kvm-unit-tests PATCH v7 10/11] arm/arm64: gicv3: add an IPI test

Signed-off-by: Andrew Jones --- v7: - add common ipi_send_single/mask (replacing ipi_send). Note, the arg order irq,cpu got swapped. [Eric] - comment rewording [Eric] - make enable_defaults a common op [Eric] - gic_enable_defaults() will now invoke gic_init if necessary [drew] - split

Re: [Qemu-devel] [kvm-unit-tests PATCH v11 1/3] arm: Add PMU test

g the newly introduced report_info() to make it look nicer. Agreed. That would look nicer and make good use of report_info. Let's do that. > > > > > Signed-off-by: Christopher Covington > > Signed-off-by: Wei Huang > >

[Qemu-devel] [kvm-unit-tests PATCH v7 05/11] arm/arm64: irq enable/disable

Reviewed-by: Alex Bennée Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- lib/arm/asm/processor.h | 10 ++ lib/arm64/asm/processor.h | 10 ++ 2 files changed, 20 insertions(+) diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h index bc46d1f980ee

[Qemu-devel] [kvm-unit-tests PATCH v7 04/11] arm/arm64: add some delay routines

Allow a thread to wait some specified amount of time. Can specify in cycles, usecs, and msecs. Reviewed-by: Alex Bennée Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- lib/arm/asm/processor.h | 19 +++ lib/arm/processor.c | 15 +++ lib/arm64/asm

Re: [Qemu-devel] [kvm-unit-tests PATCH v11 3/3] arm: pmu: Add CPI checking

TCG mode in the configuration file. > > Signed-off-by: Christopher Covington > Signed-off-by: Wei Huang > --- > arm/pmu.c | 123 > +- > arm/unittests.cfg | 14 +++ > 2 files changed, 136 insertions(+), 1 deletion(-) Reviewed-by: Andrew Jones

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