On Tue, Nov 22, 2016 at 12:29:11PM -0600, Wei Huang wrote:
> Changes from v10:
> * Change the name of loop test function to precise_instrs_loop()
> * Minor comment fixes to measure_instrs() and to explain isb() in loop funcs
>
> Note:
> 1) Current KVM code has bugs in handling PMCCFILTR write. A
On Thu, Nov 24, 2016 at 10:54:35AM +0100, Auger Eric wrote:
> Hi Drew,
>
> On 23/11/2016 17:54, Andrew Jones wrote:
> > Reviewed-by: Alex Bennée
> > Reviewed-by: Eric Auger
> > Signed-off-by: Andrew Jones
> >
> > ---
> > v7: split lib/arm/gic.
On Thu, Nov 24, 2016 at 10:54:55AM +0100, Auger Eric wrote:
> Hi Drew,
>
> On 23/11/2016 17:54, Andrew Jones wrote:
> > Signed-off-by: Andrew Jones
> >
> > ---
> > v7:
> > - add common ipi_send_single/mask (replacing ipi_send).
> >N
On Thu, Nov 24, 2016 at 10:57:01AM +0100, Auger Eric wrote:
> Hi,
>
> On 23/11/2016 17:54, Andrew Jones wrote:
> > Allow user to select who sends ipis and with which irq,
> > rather than just always sending irq=0 from cpu0.
> >
> > Signed-off-by: Andrew Jo
On Fri, Nov 25, 2016 at 12:32:24PM +, Andre Przywara wrote:
> Hi Drew,
>
>
>
> On 23/11/16 17:15, Andrew Jones wrote:
> >>> +
> >>> +#if defined(__arm__)
> >>
> >> I guess you should use the arch specific header files we have in
On Thu, Nov 24, 2016 at 04:10:23PM +, Alex Bennée wrote:
> While tests can be pegged to tcg it is useful to override this from time
> to time, especially when testing correctness on real systems.
> ---
> run_tests.sh | 8 ++--
> scripts/runtime.bash | 4
> 2 files changed, 10
On Thu, Nov 24, 2016 at 04:10:24PM +, Alex Bennée wrote:
> Certainly during development of the tests and MTTCG there are times when
> the timeout just gets in the way.
>
> Signed-off-by: Alex Bennée
> ---
> run_tests.sh | 8 ++--
> scripts/runtime.bash | 4
> 2 files changed
On Thu, Nov 24, 2016 at 04:10:25PM +, Alex Bennée wrote:
> This introduces a the option -o for passing of options directly to QEMU
> which is useful. In my case I'm using it to toggle MTTCG on an off:
>
> ./run_tests.sh -t -o "-tcg mttcg=on"
>
> Signed-off-by: Alex Bennée
> ---
> run_test
On Thu, Nov 24, 2016 at 04:10:26PM +, Alex Bennée wrote:
> So we can have portable formatting of uint32_t types.
>
> Signed-off-by: Alex Bennée
> ---
> lib/libcflat.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/lib/libcflat.h b/lib/libcflat.h
> index bdcc561..6dab5be 10064
On Thu, Nov 24, 2016 at 04:10:28PM +, Alex Bennée wrote:
> As distro compilers move towards defaults for build hardening for things
> like ASLR we need to force -fno-pic. Failure to do can lead to weird
> relocation problems when we build our "lat" binaries.
>
> Signed-off-by: Alex Bennée
> -
On Thu, Nov 24, 2016 at 04:10:29PM +, Alex Bennée wrote:
> This adds a fairly brain dead torture test for TLB flushes intended for
> stressing the MTTCG QEMU build. It takes the usual -smp option for
> multiple CPUs.
>
> By default it CPU0 will do a TLBIALL flush after each cycle. You can
> pa
On Thu, Nov 24, 2016 at 04:10:30PM +, Alex Bennée wrote:
> This test is the cousin of the tlbflush-code test. Instead of flushing
> running code it re-maps virtual addresses while a buffer is being filled
> up. It then audits the results checking for writes that have ended up in
> the wrong pla
On Thu, Nov 24, 2016 at 04:10:31PM +, Alex Bennée wrote:
> This test has been written mainly to stress multi-threaded TCG behaviour
> but will demonstrate failure by default on real hardware. The test takes
> the following parameters:
>
> - "lock" use GCC's locking semantics
> - "atomic" u
On Thu, Nov 24, 2016 at 04:10:22PM +, Alex Bennée wrote:
> Hi,
>
> Looking at my records it seems as though it has been a while since I
> last posted these tests. As I'm hoping to get the final bits of MTTCG
> merged upstream on the next QEMU development cycle I've been re-basing
> these and g
On Thu, Nov 24, 2016 at 04:10:22PM +, Alex Bennée wrote:
> Hi,
>
> Looking at my records it seems as though it has been a while since I
> last posted these tests. As I'm hoping to get the final bits of MTTCG
> merged upstream on the next QEMU development cycle I've been re-basing
> these and g
On Mon, Nov 28, 2016 at 11:14:48AM +, Peter Maydell wrote:
> On 28 November 2016 at 11:12, Alex Bennée wrote:
> >
> > Andrew Jones writes:
> >> I've skimmed over everything looking at it from a framwork/sytle
> >> perspective. I didn't dig in tryi
On Mon, Nov 28, 2016 at 01:30:54PM +, Peter Maydell wrote:
> On 28 November 2016 at 11:58, Andrew Jones wrote:
> > On Mon, Nov 28, 2016 at 11:14:48AM +, Peter Maydell wrote:
> >> On 28 November 2016 at 11:12, Alex Bennée wrote:
> >> >
> >> >
On Mon, Nov 28, 2016 at 03:04:45PM +0100, Andrew Jones wrote:
> On Mon, Nov 28, 2016 at 01:30:54PM +, Peter Maydell wrote:
> > On 28 November 2016 at 11:58, Andrew Jones wrote:
> > > On Mon, Nov 28, 2016 at 11:14:48AM +, Peter Maydell wrote:
> > >> On 2
On Tue, Nov 29, 2016 at 10:17:46PM +0800, Fam Zheng wrote:
> On Tue, 11/29 14:27, Paolo Bonzini wrote:
> >
> >
> > On 29/11/2016 14:24, Fam Zheng wrote:
> > > On Tue, 11/29 12:17, Paolo Bonzini wrote:
> > >>
> > >>
> > >> On 29/11/2016 11:32, Fam Zheng wrote:
> > >>>
> > >>> The kernel change wil
On Tue, Nov 29, 2016 at 11:39:44PM +0800, Fam Zheng wrote:
> On Tue, 11/29 16:24, Andrew Jones wrote:
> > On Tue, Nov 29, 2016 at 10:17:46PM +0800, Fam Zheng wrote:
> > > On Tue, 11/29 14:27, Paolo Bonzini wrote:
> > > >
> > > >
> > > > On 2
On Tue, Nov 29, 2016 at 05:13:27PM +0100, Paolo Bonzini wrote:
>
>
> On 29/11/2016 17:01, Andrew Jones wrote:
> > OK, it may be due to scheduling then. Below is the test case (for AArch64)
> > Also, I forgot to mention before that I can only see this with TCG, not
> >
On Wed, Nov 30, 2016 at 07:19:12AM +, Peter Maydell wrote:
> On 29 November 2016 at 19:38, Andrew Jones wrote:
> > Thanks for making me look, I was simply assuming we were in the while
> > loops above.
> >
> > I couldn't get the problem to reproduce with a
Should this be From: Andre?
On Wed, Nov 30, 2016 at 11:16:39PM -0600, Wei Huang wrote:
> This patch defines four macros to assist creating system register
> accessors under both ARMv7 and AArch64:
>* DEFINE_GET_SYSREG32(name, ...)
>* DEFINE_SET_SYSREG32(name, ...)
>* DEFINE_GET_SYSREG
;
> Signed-off-by: Christopher Covington
> Signed-off-by: Wei Huang
> Reviewed-by: Andrew Jones
> ---
> arm/Makefile.common | 3 ++-
> arm/pmu.c | 62
> +
> arm/unittests.cfg | 5 +
> 3 files chang
Wei Huang
> Reviewed-by: Andrew Jones
> ---
> arm/pmu.c | 94
> +++
> 1 file changed, 94 insertions(+)
>
> diff --git a/arm/pmu.c b/arm/pmu.c
> index 1fe2b1a..3566a27 100644
> --- a/arm/pmu.c
> +++ b/arm/p
TCG mode in the configuration file.
>
> Signed-off-by: Christopher Covington
> Signed-off-by: Wei Huang
> Reviewed-by: Andrew Jones
> ---
> arm/pmu.c | 123
> +-
> arm/unittests.cfg | 14 +++
> 2 files changed,
On Thu, Dec 01, 2016 at 09:59:03AM +0100, Andrew Jones wrote:
>
> Should this be From: Andre?
>
> On Wed, Nov 30, 2016 at 11:16:39PM -0600, Wei Huang wrote:
> > This patch defines four macros to assist creating system register
> > accessors unde
On Thu, Dec 01, 2016 at 11:11:55AM +, Andre Przywara wrote:
> Hi,
>
> On 01/12/16 08:59, Andrew Jones wrote:
> >
> > Should this be From: Andre?
>
> No need from my side, this way all the bug reports are send to Wei ;-)
>
> > On Wed, Nov 30, 2016
On Thu, Dec 01, 2016 at 10:19:13AM +, Andre Przywara wrote:
> Hi Drew,
>
> actually unrelated to this actual patch, but since you mentioned it:
>
> > As we work out how best to handle tcg-only tests in order to get Alex
> > Bennee's MTTCG tests merged, we'll probably revisit this file,
>
> S
On Thu, Dec 01, 2016 at 09:27:59AM -0600, Wei Huang wrote:
>
>
> On 12/01/2016 02:59 AM, Andrew Jones wrote:
> >
> > Should this be From: Andre?
> >
> > On Wed, Nov 30, 2016 at 11:16:39PM -0600, Wei Huang wrote:
> >> This patch defines four
On Thu, Dec 01, 2016 at 11:36:55AM -0600, Wei Huang wrote:
>
>
> On 12/01/2016 03:18 AM, Andrew Jones wrote:
> > On Wed, Nov 30, 2016 at 11:16:41PM -0600, Wei Huang wrote:
> >> From: Christopher Covington
> >>
> >> Ensure that reads of the PMCCNTR_EL0 a
mpat.o
> diff --git a/lib/arm/asm/gic-v3-its.h b/lib/arm/asm/gic-v3-its.h
> new file mode 100644
> index 000..2044565
> --- /dev/null
> +++ b/lib/arm/asm/gic-v3-its.h
> @@ -0,0 +1,22 @@
> +/*
> + * All ITS* defines are lifted from include/linux/irqchip/arm-gic-v3.h
&
On Mon, Dec 05, 2016 at 10:46:36PM +0100, Eric Auger wrote:
> Add a new cpu_count field in gicv3_data indicating the
> number of redistributors. This will be useful for enumeration
> of their resources such as LPI pending tables.
I'm fine with the additional state, but just curious, will it
ever b
On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote:
> This series proposes a framework to test the virtual ITS.
> This is based on Drew's v7 series [1]. The last patch tests
> several ITS commands (collection/device mapping, interrupt
> translation service entry creation and LPI trigger thr
On Tue, Dec 06, 2016 at 11:14:41AM +, Andre Przywara wrote:
> Hi,
>
> On 06/12/16 09:48, Andrew Jones wrote:
> > On Mon, Dec 05, 2016 at 10:46:31PM +0100, Eric Auger wrote:
> >> This series proposes a framework to test the virtual ITS.
> >> This is based
ed
> with __ACCESS_CP15() or __ACCESS_CP15_64() depending if it is 32-bit or
> 64-bit. get_mpidr() is re-written with new macros.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Wei Huang
> ---
> lib/arm/asm/processor.h | 6 +++---
> lib/arm/asm/sysreg.h | 19 +++
On Tue, Dec 06, 2016 at 12:05:23PM -0600, Wei Huang wrote:
> Changes from v13:
> * Rename cp15.h to sysreg.h for ARMv7 and add a new file sysreg.h for ARMv8
> * Add macros for read_sysreg() and write_sysreg(). CP15 registers can be
> defined with __ACCESS_CP15() or __ACCESS_CP15_64(). sysreg.h (A
On Tue, Dec 06, 2016 at 12:05:26PM -0600, Wei Huang wrote:
> From: Christopher Covington
>
> Beginning with a simple sanity check of the control register, add
> a unit test for the ARM Performance Monitors Unit (PMU).
>
> Signed-off-by: Christopher Covington
> Signed-off-by: Wei Huang
> ---
>
From: Peter Xu
These macros will be useful to do page alignment checks.
Reviewed-by: Andre Przywara
Reviewed-by: Eric Auger
Signed-off-by: Peter Xu
[drew: also added SZ_64K and changed to shifts]
Signed-off-by: Andrew Jones
---
v6: change to shifts [Alex]
---
lib/libcflat.h | 6 ++
1
Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.
Signed-off-by: Andrew Jones
---
v8: rewrote basing on new sysreg framework. Also decided delay
functions warrant their own files (delay.[ch])
---
arm/Makefile.common | 1 +
lib/arm/asm
always a place it's needed.
While this change is mostly for TCG, it's fine to do for KVM as well.
The Linux kernel made the same change with 1baa82f4803 for armv8. As
the yield instruction is also available on armv7, we make the change
for both.
Signed-off-by: Andrew Jones
---
v8:
functionality needed by the later gic patches
05-06: enable gicv2 and gicv2 IPI test
07-09: enable gicv3 and gicv3 IPI test
10: extend the IPI tests to use cpu1 and irq1 instead of zero
Available here: https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic-v8
and based on https://gith
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 10 ++
lib/arm64/asm/processor.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index 857bdd96a3cc
Reviewed-by: Andre Przywara
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v8: in anticipation of get_mpidr() returning a u64 (patches will
be in a future series), make sure we use that type everywhere
get_mpidr is used
v5: left cpus a u32 for now. Changing to u64 requires a
Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.
Reviewed-by: Andre Przywara
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v6: added comments (register offset headers) [Alex]
v5: share/use only the modern register names
ender=1 is a bit limited for the
long term, as we may want to test IPIs across host sockets with
pinned vcpus. But we can improve on this later, possibly with the
introduction of a command line parameter.
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v8:
- remove crufy command line pa
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v8:
- fix check_spurious print arguments and change the printf
to a report_info
- remove the self-ipi test issued when no subtest is given,
i.e. require a subtest to be given
- use report_summary for no supported gic present
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v8: few sysreg framework and new delay rebase changes
v7: split lib/arm/gic.c into gic-v2/3.c [Eric]
v6:
- added comments [Alex]
- added stride parameter to gicv3_set_redist_base [Andre]
- redist-wait s/rwp/uwp
Signed-off-by: Andrew Jones
---
v8:
- keep the gic_common_ops concept completely local to
lib/arm/gic.c by instead exposing the more useful
concept of gic-specific functions
- sysreg rebase changes
- ordered ICC registers in spec-order (OCD kicked in...)
v7:
- add common
_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
> @@ -501,10 +508,12 @@ int kvm_arch_init_vcpu(CPUState *cs)
> if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
> cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
> }
> -if (kvm_irqchip_in_kernel() &&
> -kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) {
> -cpu->has_pmu = true;
> -cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
> +/* enable PMU based on KVM mode, hw capability, and user setting */
> +cpu->has_pmu &= kvm_irqchip_in_kernel() &&
> +kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3);
> +cpu->kvm_init_features[0] |= cpu->has_pmu << KVM_ARM_VCPU_PMU_V3;
> +if (!cpu->has_pmu) {
> +unset_feature(&env->features, ARM_FEATURE_PMU);
nit: I think I'd like the following more
if (cpu->has_pmu) {
cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
} else {
unset_feature(&env->features, ARM_FEATURE_PMU);
}
but whatever.
> }
>
> /* Do KVM_ARM_VCPU_INIT ioctl */
> --
> 1.8.3.1
>
>
With some changes to the commit message
Reviewed-by: Andrew Jones
On Wed, Sep 14, 2016 at 02:09:03AM -0400, Wei Huang wrote:
> CPU vPMU is now turned off by default, but it was ON in virt-2.7
> machine type. To solve this problem, this patch adds a PMU option
> in machine state, which is used to control CPU's vPMU status. This
> PMU option is not exposed to comma
On Wed, Sep 14, 2016 at 10:37:19AM +0200, Andrew Jones wrote:
> On Wed, Sep 14, 2016 at 02:09:03AM -0400, Wei Huang wrote:
> > CPU vPMU is now turned off by default, but it was ON in virt-2.7
> > machine type. To solve this problem, this patch adds a PMU option
> > in machine
On Thu, Sep 15, 2016 at 01:04:15AM -0400, Wei Huang wrote:
> This patch adds a pmu=[on/off] option to enable/disable vPMU support
> in guest vCPU. This option is only available for cortex-a57/cortex-53/
> host under both TCG and KVM modes, but unavailable on ARMv7 and other
> processors. It allows
_options(MachineClass *mc)
> virt_machine_2_7_options(mc);
> SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
> vmc->disallow_affinity_adjustment = true;
> + /* Disable PMU for 2.6 and down as PMU support was first introduced
> + * and enabled in 2.7.
> + */
> +vmc->pmu_default_on = false;
> }
> DEFINE_VIRT_MACHINE(2, 6)
> --
> 1.8.3.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
On Wed, Sep 07, 2016 at 10:39:28PM +0300, Marcel Apfelbaum wrote:
> On 09/07/2016 08:55 PM, Laine Stump wrote:
> > On 09/07/2016 04:06 AM, Marcel Apfelbaum wrote:
[snip]
> > > Good point, maybe libvirt can avoid adding switches unless the user
> > > explicitly
> > > asked for them. I checked and it
On Tue, Sep 20, 2016 at 10:33:52PM -0400, Wei Huang wrote:
> This patchset adds a pmu=[on/off] option to enable/disable vPMU support
> for guest VM. There are several reasons to justify this option. First,
> vPMU can be problematic for cross-migration between different SoC as perf
> counters are a
On Tue, Sep 20, 2016 at 10:33:53PM -0400, Wei Huang wrote:
> This patch adds a pmu=[on/off] option to enable/disable vPMU support
> in guest vCPU. This option is only available for cortex-a57/cortex-53/
> host under both TCG and KVM modes, but unavailable on ARMv7 and other
> processors. It allows
On Tue, Sep 20, 2016 at 10:33:54PM -0400, Wei Huang wrote:
> CPU vPMU is now turned off by default, but it was ON in virt-2.7
> machine type. To solve this problem, this patch adds a PMU option
> in machine state, which is used to control CPU's vPMU status. This
> PMU option is not exposed to comma
On Wed, Sep 21, 2016 at 08:35:41AM -0500, Wei Huang wrote:
> On 09/21/2016 02:53 AM, Andrew Jones wrote:
> > On Tue, Sep 20, 2016 at 10:33:53PM -0400, Wei Huang wrote:
[snip]
> >> +if (cpu->has_pmu == ON_OFF_AUTO_ON && !kvm_enabled()) {
> >> +
On Tue, Nov 08, 2016 at 09:48:02AM +, Andre Przywara wrote:
> Hi,
>
> this is an illustrative patch which shows what can be removed from
> the kvm-unit-tests GIC headers. If this patch finds mercy, it should be
> squashed into the in-flight GIC patches, eventually.
> The rationale for this pat
Make implementation equivalent to Linux's include/linux/stringify.h
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 72b1bf9668ef..82005f5d014f 100644
---
r and irq
Available here: https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic-v4
Andrew Jones (10):
lib: xstr: allow multiple args
arm64: fix get_"sysreg32" and make MPIDR 64bit
arm/arm64: smp: support more than 8 cpus
arm/arm64: add some delay routines
arm/arm64: irq enab
mrs is always 64bit, so we should always use a 64bit register.
Sometimes we'll only want to return the lower 32, but not for
MPIDR, as that does define fields in the upper 32.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm64/asm/processor.h
Signed-off-by: Andrew Jones
---
v4:
- heavily comment gicv3_ipi_send_tlist() [Eric]
- changes needed for gicv2 iar/irqstat fix to other patch
v2:
- use IRM for gicv3 broadcast
---
arm/gic.c | 195 ++---
arm/unittests.cfg | 6
Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 19 +++
lib/arm/processor.c | 15 +++
lib/arm64/asm
Signed-off-by: Andrew Jones
---
v4: improved commit message
---
arm/run | 19 ---
arm/selftest.c| 5 -
lib/arm/asm/processor.h | 9 +++--
lib/arm/asm/setup.h | 4 ++--
lib/arm/setup.c | 12 +++-
lib/arm64/asm
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 10 ++
lib/arm64/asm/processor.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index afc903ca7d4a
Allow user to select who sends ipis and with which irq,
rather than just always sending irq=0 from cpu0.
Signed-off-by: Andrew Jones
---
v4: improve structure and make sure spurious checking is
done even when the sender isn't cpu0
v2: actually check that the irq received was the irq
Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.
Signed-off-by: Andrew Jones
---
v4:
- only take defines from kernel we need now [Andre]
- moved defines to asm/gic.h so they'll be shared with v3 [drew]
- simplify enable b
From: Peter Xu
These macros will be useful to do page alignment checks.
Signed-off-by: Peter Xu
[drew: also added SZ_64K]
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 82005f5d014f..143fc53061fe
Signed-off-by: Andrew Jones
---
v4:
- only take defines from kernel we need now [Andre]
- simplify enable by not caring if we reinit the distributor [drew]
v2:
- configure irqs as NS GRP1
---
lib/arm/asm/arch_gicv3.h | 42 +
lib/arm/asm/gic-v3.h | 92
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v4: properly mask irqnr in ipi_handler
v2: add more details in the output if a test fails,
report spurious interrupts if we get them
---
arm/Makefile.common | 6 +-
arm/gic.c | 195
Argh. I forgot to compile/test arm32/gicv3... Just did now and found
a copy+paste error.
On Tue, Nov 08, 2016 at 09:21:38PM +0100, Andrew Jones wrote:
[...]
> diff --git a/lib/arm/asm/arch_gicv3.h b/lib/arm/asm/arch_gicv3.h
> index 81a1e5f6c29c..cbcec024a2a6 100644
> --- a/lib/arm/asm/a
On Wed, Nov 09, 2016 at 11:01:46AM +0800, Dave Young wrote:
> Hi,
>
> Latest linux kernel enabled kaslr to randomiz phys/virt memory
> addresses, we had some effort to support kexec/kdump so that crash
> utility can still works in case crashed kernel has kaslr enabled.
>
> But according to Dave A
On Wed, Nov 09, 2016 at 11:37:35AM +, Daniel P. Berrange wrote:
> On Wed, Nov 09, 2016 at 12:26:17PM +0100, Laszlo Ersek wrote:
> > On 11/09/16 11:40, Andrew Jones wrote:
> > > On Wed, Nov 09, 2016 at 11:01:46AM +0800, Dave Young wrote:
> > >> Hi,
> > &
On Wed, Nov 09, 2016 at 11:12:03AM +, Andre Przywara wrote:
[...]
> > diff --git a/lib/arm/setup.c b/lib/arm/setup.c
> > index 7e7b39f11dde..b6e2d5815e72 100644
> > --- a/lib/arm/setup.c
> > +++ b/lib/arm/setup.c
> > @@ -24,12 +24,22 @@ extern unsigned long stacktop;
> > extern void io_init(vo
t; +/*
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifndef _ASMARM_GIC_H_
> > +#define _ASMARM_GIC_H_
> > +
> > +#include
> > +
> >
On Wed, Nov 09, 2016 at 12:01:42PM +, Andre Przywara wrote:
> Hi,
>
> On 09/11/16 11:57, Andrew Jones wrote:
> > On Wed, Nov 09, 2016 at 11:12:03AM +, Andre Przywara wrote:
> > [...]
> >>> diff --git a/lib/arm/setup.c b/lib/arm/setup.c
> >>
On Wed, Nov 09, 2016 at 11:58:19AM +, Daniel P. Berrange wrote:
> On Wed, Nov 09, 2016 at 12:48:09PM +0100, Andrew Jones wrote:
> > On Wed, Nov 09, 2016 at 11:37:35AM +, Daniel P. Berrange wrote:
> > > On Wed, Nov 09, 2016 at 12:26:17PM +0100, Laszlo Ersek wrote:
> &g
@@
> > +/*
> > + * All GIC* defines are lifted from include/linux/irqchip/arm-gic-v3.h
> > + *
> > + * Copyright (C) 2016, Red Hat Inc, Andrew Jones
> > + *
> > + * This work is licensed under the terms of the GNU LGPL, version 2.
> > + */
> > +#ifnde
On Wed, Nov 09, 2016 at 02:43:53PM +, Andre Przywara wrote:
> Hi,
>
> On 09/11/16 13:08, Andrew Jones wrote:
> > On Wed, Nov 09, 2016 at 12:35:48PM +, Andre Przywara wrote:
> > [...]
> >>> diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
>
mrs is always 64bit, so we should always use a 64bit register.
Sometimes we'll only want to return the lower 32, but not for
MPIDR, as that does define fields in the upper 32.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm64/asm/processor.h
Make implementation equivalent to Linux's include/linux/stringify.h
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 72b1bf9668ef..82005f5d014f 100644
---
Allow a thread to wait some specified amount of time. Can
specify in cycles, usecs, and msecs.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 19 +++
lib/arm/processor.c | 15 +++
lib/arm64/asm
Signed-off-by: Andrew Jones
---
v4: improved commit message
---
arm/run | 19 ---
arm/selftest.c| 5 -
lib/arm/asm/processor.h | 9 +++--
lib/arm/asm/setup.h | 4 ++--
lib/arm/setup.c | 12 +++-
lib/arm64/asm
Allow user to select who sends ipis and with which irq,
rather than just always sending irq=0 from cpu0.
Signed-off-by: Andrew Jones
---
v4: improve structure and make sure spurious checking is
done even when the sender isn't cpu0
v2: actually check that the irq received was the irq
r and irq
Available here: https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic-v4
Andrew Jones (10):
lib: xstr: allow multiple args
arm64: fix get_"sysreg32" and make MPIDR 64bit
arm/arm64: smp: support more than 8 cpus
arm/arm64: add some delay routines
arm/arm64: irq enab
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 10 ++
lib/arm64/asm/processor.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index afc903ca7d4a
Signed-off-by: Andrew Jones
---
v4:
- heavily comment gicv3_ipi_send_tlist() [Eric]
- changes needed for gicv2 iar/irqstat fix to other patch
v2:
- use IRM for gicv3 broadcast
---
arm/gic.c | 195 ++---
arm/unittests.cfg | 6
Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.
Signed-off-by: Andrew Jones
---
v4:
- only take defines from kernel we need now [Andre]
- moved defines to asm/gic.h so they'll be shared with v3 [drew]
- simplify enable b
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v4: properly mask irqnr in ipi_handler
v2: add more details in the output if a test fails,
report spurious interrupts if we get them
---
arm/Makefile.common | 6 +-
arm/gic.c | 195
Signed-off-by: Andrew Jones
---
v4:
- only take defines from kernel we need now [Andre]
- simplify enable by not caring if we reinit the distributor [drew]
v2:
- configure irqs as NS GRP1
---
lib/arm/asm/arch_gicv3.h | 42 +
lib/arm/asm/gic-v3.h | 92
From: Peter Xu
These macros will be useful to do page alignment checks.
Signed-off-by: Peter Xu
[drew: also added SZ_64K]
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 82005f5d014f..143fc53061fe
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/arm/asm/processor.h | 10 ++
lib/arm64/asm/processor.h | 10 ++
2 files changed, 20 insertions(+)
diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h
index bc46d1f980ee
Add some gicv2 support. This just adds init and enable
functions, allowing unit tests to start messing with it.
Signed-off-by: Andrew Jones
---
v5: share/use only the modern register names [Andre]
v4:
- only take defines from kernel we need now [Andre]
- moved defines to asm/gic.h so they&#x
he real v5 is coming...
Thanks,
Your Friendly Spammer
>
> Cheers,
> Andre.
>
> On 10/11/16 16:07, Andrew Jones wrote:
> > v4:
> > - Eric's r-b's
> > - Andre's suggestion to only take defines we need
> > - several other changes listed in in
Make implementation equivalent to Linux's include/linux/stringify.h
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
lib/libcflat.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/libcflat.h b/lib/libcflat.h
index 72b1bf9668ef..82005f5d014f 100644
---
08-10: enable gicv3 and gicv3 IPI test
11: extend the IPI tests to take variable sender and irq
Available here: https://github.com/rhdrjones/kvm-unit-tests/commits/arm/gic-v5
Andrew Jones (10):
lib: xstr: allow multiple args
arm64: fix get_"sysreg32" and make MPIDR 64bit
arm
Signed-off-by: Andrew Jones
---
v5: use modern register names [Andre]
v4:
- only take defines from kernel we need now [Andre]
- simplify enable by not caring if we reinit the distributor [drew]
v2:
- configure irqs as NS GRP1
---
lib/arm/asm/arch_gicv3.h | 42 +
lib/arm
mrs is always 64bit, so we should always use a 64bit register.
Sometimes we'll only want to return the lower 32, but not for
MPIDR, as that does define fields in the upper 32.
Reviewed-by: Alex Bennée
Reviewed-by: Eric Auger
Signed-off-by: Andrew Jones
---
v5: switch arm32's ge
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