: John Platts
Signed-off-by: Shivaprasad G Bhat
Reviewed-by: Lucas Mateus Castro
Reviewed-by: Cédric Le Goater
Message-Id:
<168319294881.1159309.17060400720026083557.st...@ltc-boston1.aus.stglabs.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
tests/tcg/ppc64/Makefile.targe
The following changes since commit a9fe9e191b4305b88c356a1ed9ac3baf89eb18aa:
Merge tag 'pull-riscv-to-apply-20230505-1' of
https://github.com/alistair23/qemu into staging (2023-05-05 09:25:13 +0100)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-2
From: Harsh Prateek Bora
Would like to get notified of changes in this area and review them.
Signed-off-by: Harsh Prateek Bora
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230503093619.2530487-3-hars...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
MAINTAINERS |
On 5/18/23 23:19, Weiwei Li wrote:
Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
include/disas/dis-asm.h | 2
ese copyrights but it would be good to have a 2023
copyright
as well since the file was just created.
Other than that:
Reviewed-by: Daniel Henrique Barboza
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General P
case 3: op = rv_op_cm_mva01s; break;
+if (dec->cfg->ext_zcmp) {
+switch ((inst >> 5) & 0b011) {
+case 1: op = rv_op_cm_mvsa01; break;
+ case 3
On 5/18/23 23:19, Weiwei Li wrote:
Support disas for Z*inx instructions only when Zfinx extension is supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
disas/riscv.c | 16
1 file changed, 12 insertions(+), 4
mechanical patch. I'll trust that you used a form of
search/replace to do these changes and the order of the entries wasn't
changed.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/ris
In fact, apparently checkpatch.pl is not too happy about this patch:
On 5/18/23 23:19, Weiwei Li wrote:
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 20
1 file
On 5/18/23 23:19, Weiwei Li wrote:
Remove redundant parenthese and fix multi-line comments.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
disas/riscv.c | 219 +-
1 file changed, 110
On 5/18/23 23:19, Weiwei Li wrote:
Fix lines with over 80 characters.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
disas/riscv.c | 201 +++---
1 file changed, 140 insertions(+), 61
Henrique Barboza
hw/riscv/opentitan.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index bc678766e7..2d21ee39c5 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -75,7 +75,7 @@ static const MemMapEntry
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
QOM type names are usually defined as TYPE_FOO.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 2 +-
2 files changed, 3 insertions
an_machine_init().
Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine")
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
include/hw/riscv/opentitan.h | 3 ++-
hw/riscv/opentitan.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletion
On 5/20/23 02:45, Philippe Mathieu-Daudé wrote:
Expand the DEFINE_MACHINE() macro, converting the class_init()
handler.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
include/hw/riscv/opentitan.h | 3 ++-
hw/riscv/opentitan.c | 10
in a pair of commits.
I wonder whether we should forbid type_init()/type_register_static() and
force everyone to use DEFINE_TYPES(). We need less options when dealing
with QOM.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Philippe Mathieu-Daudé
---
hw/riscv/opentitan.c | 21
On 5/22/23 11:27, Weiwei Li wrote:
On 2023/5/22 21:10, Daniel Henrique Barboza wrote:
In fact, apparently checkpatch.pl is not too happy about this patch:
On 5/18/23 23:19, Weiwei Li wrote:
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by
On 5/18/23 08:38, Rajnesh Kanwal wrote:
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to
On 5/18/23 08:38, Rajnesh Kanwal wrote:
This change adds support for inserting virtual interrupts from HS-mode
into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering
from HS-mode.
Also, the spec doesn't mandate the interrupt to be actually supported
in hardware. Which allow
On 5/23/23 06:35, Weiwei Li wrote:
Split RISCVCPUConfig declarations to prepare for passing it to disas.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.h | 114 +-
target/riscv
!
Suggested-by: Daniel Henrique Barboza
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
scripts/checkpatch.pl | 6 ++
1 file changed, 6 insertions(+)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index eeaec436eb..db8029635c 100755
--- a/scripts
qemu_mutex_unlock_iothread();
+}
'locked' is not a good named for this flag because you guaranteed that the
iothread
will always be locked at this point. Questions is whether you locked it
yourself,
and then you need to unlock it, or if it was locked beforehand.
I suggest renaming 'locked' to 'release_lock' for clarity. Asumming you agree:
Reviewed-by: Daniel Henrique Barboza
+}
+
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *),
void *arg)
{
On 5/22/23 10:11, Tommy Wu wrote:
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 11 ++
target/riscv/csr.c | 82
On 5/22/23 10:11, Tommy Wu wrote:
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu_helper.c | 60 +++
1 file changed, 55 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index cc789
On 5/22/23 10:11, Tommy Wu wrote:
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode| 3 ++
.../riscv/insn_trans/trans_privileged.c.inc | 12 +
target/riscv/op_helper.c
On 5/15/23 13:02, Nicholas Piggin wrote:
The behaviour of the Address Translation Mode on Interrupt resource is
not consistently supported by all CPU versions or all KVM versions: KVM
HV does not support mode 2, and does not support mode 3 on POWER7 or
early POWER9 processesors. KVM PR only su
pci_realize_and_unref() in board code. Fix this by initializing s->cpu_intr
before realizing the south bridge.
Fixes: cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder")
Signed-off-by: Bernhard Beschow
---
Reviewed-by: Daniel Henrique Barboza
And queued in ppc-next.
On 5/26/23 04:38, Cédric Le Goater wrote:
From: Alexander Bulekov
As lpc-hc is designed for re-entrant calls from xscom, mark it
re-entrancy safe.
Reported-by: Thomas Huth
Signed-off-by: Alexander Bulekov
[clg: mark opb_master_regs as re-entrancy safe also ]
Signed-off-by: Cédric Le Goate
does not really matter to QEMU (because it does not care
about SMT mode in the target), but for consistency all PVRs should use
the same chip type. We'll go with the SMT4 OpenPOWER type.
Signed-off-by: Nicholas Piggin
---
Reviewed-by: Daniel Henrique Barboza
And queued. Thanks,
Daniel
On 5/15/23 06:26, Nicholas Piggin wrote:
Hopefully these are getting close to ready now. There is still the
question about doing better with adding test cases for all this, I
haven't exactly got a good answer yet but I do have kvm-unit-tests
for most at least.
Patches 1 and 4 queued to ppc-n
On 5/23/23 17:25, Richard Henderson wrote:
Instead of computing an artifical "class" bitmask then
converting that to the fprf value, compute the final
value from the start.
Reorder the tests to check the most likely cases first.
Queued in ppc-next ("artifical" typo fixed).
Thanks,
Daniel
On 5/15/23 13:02, Nicholas Piggin wrote:
POWER9 DD2.1 and earlier had significant limitations when running KVM,
including lack of "mixed mode" MMU support (ability to run HPT and RPT
mode on threads of the same core), and a translation prefetch issue
which is worked around by disabling "AIL" m
match that now that it was
confirmed to work better with AmigaOS.
Signed-off-by: BALATON Zoltan
Tested-by: Rene Engel
---
Reviewed-by: Daniel Henrique Barboza
And queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
hw/ppc/pegasos2.c | 2 +-
1 file changed, 1 insertion(
The following changes since commit ac84b57b4d74606f7f83667a0606deef32b2049d:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2023-05-26 14:40:55 -0700)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20230528
for you to f
, it
does not try to implement finer details of SPR implementation (e.g.,
not all bits implemented as simple read/write storage).
Signed-off-by: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
Message-Id: <20230515092655.171206-2-npig...@gmail.com>
Signed-off-by: Daniel Henrique B
supported.
KVM has a cap to advertise support for AIL-3.
Reviewed-by: David Gibson
Signed-off-by: Nicholas Piggin
Message-Id: <20230515160216.394612-1-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr.c | 7 +++
hw/ppc/spapr_caps.c
lex Bennée
Message-Id: <20230523202507.688859-1-richard.hender...@linaro.org>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/fpu_helper.c | 78 -
1 file changed, 22 insertions(+), 56 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/
() in board code. Fix this by initializing s->cpu_intr
before realizing the south bridge.
Fixes: cef2e7148e32 ("hw/isa/i82378: Remove intermediate IRQ forwarder")
Signed-off-by: Bernhard Beschow
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230304114043.121024-4-shen...
of registers modified
by the Alignment interrupt.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
Message-Id: <20230515092655.171206-5-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 17 ++---
1 file changed, 10 insertions
r to QEMU (because it does not care
about SMT mode in the target), but for consistency all PVRs should use
the same chip type. We'll go with the SMT4 OpenPOWER type.
Signed-off-by: Nicholas Piggin
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230515160131.394562-1-npig...@gmail.com&g
: Thomas Huth
Message-Id: <20230526073850.2772197-1-...@kaod.org>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv_lpc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 01f44c19eb..605d390861 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv
t was
confirmed to work better with AmigaOS.
Signed-off-by: BALATON Zoltan
Tested-by: Rene Engel
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20230528152937.b8dad746...@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pegasos2.c | 2 +-
1 file changed, 1 inse
libm code. It doesn't have
the fallback for 3.0 onwards to match hardware behaviour.
Signed-off-by: Richard Purdie
Reviewed-by: Matheus Ferst
Reviewed-by: Richard Henderson
Message-Id: <20230510111913.1718734-1-richard.pur...@linuxfoundation.org>
Signed-off-by: Daniel Henri
Prateek Bora
Message-Id: <20230515160201.394587-1-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pnv.c | 2 +-
hw/ppc/pnv_core.c | 2 +-
hw/ppc/spapr.c | 2 +-
hw/ppc/spapr_cpu_core.c| 1 +
include/hw/ppc/pnv.h |
On 5/28/23 14:36, Michael Tokarev wrote:
28.05.2023 19:49, Daniel Henrique Barboza wrote:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20230528
ppc patch queue for 2023-05-28:
This queue includes several assorted fixes for PowerPC SPR
emulation, a change in the default Pegasos2
On 3/8/23 09:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
Signed-off-by: Yi Chen
---
target/riscv/csr.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions
d defaults from this
function. This is not the case since commit 26b2bc58599c ("target/riscv:
Don't expose the CPU properties on names CPUs"), but given that this is
also a possibility, clarify in the function that using this function
will overwrite existing values in cpu->cfg
put in a separated function to enhance the
readability of riscv_cpu_validate_set_extensions().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 83 ++
1 file changed, 47 insertions(+), 36 deletions(-)
diff --git a/target/riscv/cpu.c b/target
set extensions after;
- RVE is now forbidden in all validations, not just in write_misa();
- RVG is now forbidden in write_misa();
- write_misa now uses set_misa() and validate_set_extensions().
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html
Daniel Henrique Barboza (17):
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c
that
any future change in MISA RV* bits should also be reflected in the
helpers as well.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 120 -
target/riscv/cpu.h | 3 +-
2 files changed, 65 insertions(+), 58 deletions(-)
diff --git a/targ
bits
(icsr and ifencei). These would be 2 extra states that we would need to
store to fallback from a validation failure.
Since write_misa() is still on experimental state let's make our lives
easier for now and disable RVG updates.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/csr
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5060a98b6d..0baed79
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0baed79
is - next patch
has plans for it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4988fd4d4b..48838471b8 100644
--- a/target/riscv/cpu.c
+++ b/target/r
Center all validations that are scattered in riscv_cpu_realize() in the
same function.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 74 ++
1 file changed, 35 insertions(+), 39 deletions(-)
diff --git a/target/riscv/cpu.c b/target
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid
setting it for write_misa(). Add it so we can gate write_misa() properly
against it.
Signed-off-by: Daniel Henrique Barboza
---
target/
init().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 60 --
1 file changed, 48 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e2cd55320c..499738d2dd 100644
--- a/target/riscv/cpu.c
+++ b/targe
the hart.
Let's keep write_misa() as experimental for now until this logic gains
enough mileage.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +++---
target/riscv/cpu.h | 2 ++
target/riscv/csr.c | 53 +-
3 files changed,
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 40
target/riscv/cpu.h | 4 ++--
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dc6e444219..08bdf861db 100644
--- a/target/riscv/cpu
Henrique Barboza
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 964817b9d2..62ef11180f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -338,7 +338,7 @@ static void
Put all the env->priv_spec related validation into a helper to unclog
riscv_cpu_realize a bit.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 81 ++
1 file changed, 46 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.
sa_ext_mask to 'ext'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 499738d2dd..dc6e444219 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -
led by
the spec rula by accident.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a564de01df..49f0fd2c11 100644
--- a/target/riscv/cpu.c
+++ b/target/r
On 3/9/23 03:11, LIU Zhiwei wrote:
On 2023/2/23 2:51, Daniel Henrique Barboza wrote:
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR
On 3/8/23 20:00, Richard Henderson wrote:
On 3/8/23 12:19, Daniel Henrique Barboza wrote:
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
};
+#define PRIV_VERSION_LATEST PRIV_VERSION_1_12_0
Any reason not to make this a enumeration value:
PRIV_VERSION_LATEST
On 3/9/23 04:28, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
The setter is doing nothing special. Just set env->priv_ver directly.
IMHO, No better than the older implementation.
In the current context having a setter means that the function is doing
something e
On 3/9/23 04:10, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or
On 3/9/23 04:27, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC
On 3/9/23 04:40, LIU Zhiwei wrote:
On 2023/3/9 15:27, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa
On 3/9/23 04:13, Weiwei Li wrote:
Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu_helper.c | 9 -
target/riscv/csr.c| 40
On 3/9/23 04:13, Weiwei Li wrote:
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/pmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 6 +++---
target/riscv/cpu.h | 3 ++-
target/riscv/cpu_helper.c | 8
target/riscv/csr.c | 35 +++
target/riscv/pmu.c | 6 +++---
target/riscv
On 3/9/23 04:13, Weiwei Li wrote:
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 12
1 file changed, 4 insertions(+), 8
Just realized that the subject doesn't mention 'riscv' anywhere.
Yes, this is target/riscv specific. I'll make sure to mention that in the
future versions.
Thanks,
Daniel
On 3/8/23 17:19, Daniel Henrique Barboza wrote:
Hi,
During the review of a series that
Hi,
First, all patches in QEMU must also go to to the general mailing list
(qemu-devel)
as well. I'm adding it in the CC in this reply. Sorry to not mentioning it in
the
first version - I noticed that you didn't CC qemu-devel here, and in v1, just
now
when replying to this patch.
As for the c
On 3/12/23 23:18, Hang Xu wrote:
Because the starting address of ram is not necessarily 0,
the remaining free space in ram is
ram_size - (start - ram_base) instead of ram_size-start.
Signed-off-by: Hang Xu
---
Reviewed-by: Daniel Henrique Barboza
hw/riscv/boot.c| 19
On 3/13/23 12:49, Anup Patel wrote:
On Mon, Mar 13, 2023 at 7:49 AM Hang Xu wrote:
Because the starting address of ram is not necessarily 0,
the remaining free space in ram is
ram_size - (start - ram_base) instead of ram_size-start.
Signed-off-by: Hang Xu
What happens in-case a platform
the code a bit.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 86 ++
1 file changed, 49 insertions(+), 37 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..18591aa53a 100644
--- a/target/riscv/cpu
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff
generic_cpu_props(). This will leave
only a single place where there's a cpu->cfg change that needs to be
converted back to env->misa_ext*: right after disabling priv spec
extensions, at the end of riscv_cpu_validate_set_extensions(). We'll
deal with it shortly.
Signed-off-by: Dan
init().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 60 --
1 file changed, 48 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fef55d7d79..c7b6e7b84b 100644
--- a/target/riscv/cpu.c
+++ b/targe
ill prepare the function to be used in write_misa() where we won't
have an updated cpu->cfg object to work with. riscv_cpu_validate_v() is
changed to receive a const pointer to the cpu->cfg object via
riscv_cpu_cfg().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 3
on in write_misa() does not require commit changes to cpu->cfg
beforehand
- v1 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg03219.html
[1] https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg03219.html
Daniel Henrique Barboza (26):
target/riscv/cpu.c: add riscv_cpu_validate_v
done. While we're at it, create a
riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related
validation to unclog riscv_cpu_realize a bit.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 91 --
1 file changed, 56 i
riscv_cpu_validate_v() consists of checking RVV related attributes, such
as vlen and elen, and setting env->vext_spec.
This can be done during riscv_cpu_validate_misa_ext() time, allowing us
to fail earlier if RVV constrains are not met.
Signed-off-by: Daniel Henrique Barboza
---
target/ri
that
any future change in MISA RV* bits should also be reflected in the
helpers as well.
We'll want to keep env->misa_ext changes in sync with cpu->cfg during
realize() in the next patches, and both helpers will have a role to play
in that.
Signed-off-by: Daniel Henrique Barboza
---
targe
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
---
target/
ff-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a298e5e55..7458845fec 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -916,6 +916,15 @@ static
for
write_misa() later on.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 55 +-
1 file changed, 40 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 48ad7372b9..133807e39f 100644
--- a/target/ri
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2752efe
endency in riscv_cpu_validate_misa_ext() to fail
earlier.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 83b1b874ee..fa1954a850 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
sa_ext_mask to 'ext'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c7b6e7b84b..36c55abda0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
Similar to what we did with riscv_cpu_validate_misa_ext(), let's read
all MISA bits from a misa_ext val instead of reading from the cpu->cfg
object.
This will allow write_misa() to use riscv_cpu_validate_extensions().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cp
thing at once when a new priv version is
available.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 2 ++
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 18032dfd4e..1ee322001b 100644
nv->misa_ext isn't touched during validation,
but write_misa() will use it to keep cpu->cfg in sync with the new
env->misa_ext value.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 16 ++--
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 3 +--
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid
setting it for write_misa(). Add it so we can gate write_misa() properly
against it.
Signed-off-by: Daniel Henrique Barboza
---
target/
where more
cpu->cfg properties are set and disabling of extensions due to priv spec
happens. We're already validated everything we wanted, so any cpu->cfg
change made here is valid.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 13 +
1 file changed, 9 i
he write operation.
Let's keep write_misa() as experimental for now until this logic gains
enough mileage.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 12 +---
target/riscv/cpu.h | 6 ++
target/riscv/csr.c | 47 +-
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 18591aa53a..2752efe
1101 - 1200 of 5654 matches
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