Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 66
target/riscv/vector_helper.c| 130
4 files changed, 273
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 33
target/riscv/vector_helper.c| 221
4 files changed, 303 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 22 ++
target/riscv/vector_helper.c| 31 +
4 files changed, 59 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 28 +
4 files changed, 62
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 33 +
target/riscv/vector_helper.c| 20 +++
4 files changed, 59 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 26 +
target/riscv/vector_helper.c| 15 ++
4 files changed, 47 insertions
ault value is 64 bit.
vext_spec is the vector specification version, default value is v0.7.1.
These properties can be specified with other values.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 44 +++-
target/riscv/cpu.h | 2 ++
2 files changed, 45
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 21
target/riscv/vector_helper.c| 26 +
4 files changed, 54
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 23 +
target/riscv/vector_helper.c| 68 +
4 files changed, 103 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvv.inc.c | 17 +++
target/riscv/vector_helper.c| 136
4 files changed, 177 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 47 +
target/riscv/vector_helper.c| 36 +++
4 files changed, 94
the base effective address. It can been seen as a special
case of strided operations.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 6 +
target/riscv/helper.h | 105 ++
target/riscv/insn32.decode | 32 ++
target/riscv/insn_trans
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49
target/riscv/insn32.decode | 16 +++
target/riscv/insn_trans/trans_rvv.inc.c | 154
target/riscv/vector_helper.c| 112 +
4 files changed, 331
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 147
4 files changed, 198 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 ++
target/riscv/vector_helper.c| 278
4 files changed, 337 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 129
4 files changed, 158 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 48 +
4 files changed, 76 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 37 +++
target/riscv/vector_helper.c| 40 +
4 files changed, 84
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 7 +++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 11 +++
4 files changed, 24 insertions(+)
diff --git a/target
for no-fault operations in linux user mode.
* generation atomic exit exception when in parallel environment.
* fixup a lot of concrete bugs.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (60):
target/riscv: add vector
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 +
4 files changed, 84 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 103
4 files changed, 118 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files changed, 33 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 228
4 files changed, 311 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +++
target/riscv/vector_helper.c| 45 +
4 files changed, 103
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 10 +++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 5
target/riscv/vector_helper.c| 39 +
4 files changed, 58 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 23 +
target/riscv/vector_helper.c| 66 +
4 files changed, 96 insertions(+)
diff
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 35 +++
target/riscv/insn32.decode
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
target/riscv/vector_helper.c| 14
4 files changed, 124 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 44 +
target/riscv/vector_helper.c| 82 +
4 files changed, 160
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 88 +
4 files changed, 139 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 131
target/riscv/vector_helper.c| 77 ++
4 files changed, 233 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 76 +
4 files changed, 109 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 11 +++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +
target/riscv/vector_helper.c| 42 +
4 files changed
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 71 +
4 files changed, 122 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 24 ++
target/riscv/vector_helper.c| 58 +
4 files changed, 94 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 107
target/riscv/vector_helper.c| 89
4 files changed, 217
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 128
4 files changed, 155 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++
target/riscv/vector_helper.c| 28 +
4 files changed, 45 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 40 +
4 files changed, 85
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 20
4 files changed, 55 insertions
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 108 ++
target/riscv/vector_helper.c| 140
4 files changed, 291
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c| 51 +
4 files changed, 96 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 109
4 files changed, 140 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 6 ++
target/riscv/vector_helper.c| 27 +
4 files changed, 50 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 62 +
4 files changed, 70 insertions(+)
diff --git
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 17 ++
target/riscv/vector_helper.c| 76 +
4 files changed, 134 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 32 +
target/riscv/vector_helper.c| 19 +++
4 files changed, 54 insertions
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74 +
4 files changed, 125 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvv.inc.c | 9 +
target/riscv/vector_helper.c| 45 +
4 files changed, 83 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 22 +++
target/riscv/insn32.decode | 7 +
target/riscv/insn_trans/trans_rvv.inc.c | 9 ++
target/riscv/vector_helper.c| 180
4 files changed, 218 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 84 +
4 files changed, 119 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 6 +
target/riscv/vector_helper.c| 33 +
4 files changed, 56 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c| 50 +
4 files changed, 58 insertions(+)
diff --git
On 2020/2/28 3:36, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb)
+GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t
On 2020/2/28 3:17, Richard Henderson wrote:
On 2/25/20 2:35 AM, LIU Zhiwei wrote:
+static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
+{
+int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+
+return !((s->lmul == 0x3 && widen) || (reg
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 5 +
target/riscv/insn_trans/trans_rvv.inc.c | 7 ++
target/riscv/vector_helper.c| 129
4 files changed, 158 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 +++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.inc.c | 4 +
target/riscv/vector_helper.c| 103
4 files changed, 118 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 128
4 files changed, 155 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 24 ++
target/riscv/vector_helper.c| 58 +
4 files changed, 94 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49 +
target/riscv/insn32.decode | 16 ++
target/riscv/insn_trans/trans_rvv.inc.c | 18 ++
target/riscv/vector_helper.c| 228
4 files changed, 311 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c| 76 +
4 files changed, 109 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 5 +
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4
target/riscv/vector_helper.c| 22 ++
4 files changed, 33 insertions(+)
diff --git
vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
should update after configure instructions. The (ill, lmul, sew ) of vtype
and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
Signed-off-by: LIU Zhiwei
---
target/riscv/Makef
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 49
target/riscv/insn32.decode | 16 +++
target/riscv/insn_trans/trans_rvv.inc.c | 154
target/riscv/vector_helper.c| 112 +
4 files changed, 331
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17 +
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10 +++
target/riscv/vector_helper.c| 84 +
4 files changed, 119 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 19 +
target/riscv/insn32.decode | 6 +++
target/riscv/insn_trans/trans_rvv.inc.c | 8
target/riscv/vector_helper.c| 51 +
4 files changed, 84 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 12 +++
target/riscv/vector_helper.c| 28 +
4 files changed, 45 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvv.inc.c | 28 +
target/riscv/vector_helper.c| 40 +
4 files changed, 85
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 +++
target/riscv/insn32.decode | 3 ++
target/riscv/insn_trans/trans_rvv.inc.c | 37 +++
target/riscv/vector_helper.c| 40 +
4 files changed, 84
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 10 +
target/riscv/insn_trans/trans_rvv.inc.c | 16 ++
target/riscv/vector_helper.c| 278
4 files changed, 337 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 +++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.inc.c | 10
target/riscv/vector_helper.c| 74 +
4 files changed, 125 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16 +
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 7
target/riscv/vector_helper.c| 48 +
4 files changed, 76 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++
target/riscv/vector_helper.c| 51 +
4 files changed, 96 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 17
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 ++
target/riscv/vector_helper.c| 109
4 files changed, 140 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 37
target/riscv/insn32.decode | 12 ++
target/riscv/insn_trans/trans_rvv.inc.c | 33
target/riscv/vector_helper.c| 221
4 files changed, 303 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 108 ++
target/riscv/vector_helper.c| 140
4 files changed, 291
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 57 +++
target/riscv/insn32.decode | 20
target/riscv/insn_trans/trans_rvv.inc.c | 66
target/riscv/vector_helper.c| 130
4 files changed, 273
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 6 +
target/riscv/vector_helper.c| 33 +
4 files changed, 56 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 4
target/riscv/insn_trans/trans_rvv.inc.c | 6 ++
target/riscv/vector_helper.c| 27 +
4 files changed, 50 insertions
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 11 +++
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvv.inc.c | 42 +
target/riscv/vector_helper.c| 42 +
4 files changed
The v0.7.1 specification does not define vector status within mstatus.
A future revision will define the privileged portion of the vector status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_bits.h | 15 +
target/riscv/csr.c | 75 -
2 files
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c | 7 +++
target/riscv
The unit-stride fault-only-fault load instructions are used to
vectorize loops with data-dependent exit conditions(while loops).
These instructions execute as a regular load except that they
will only take a trap on element 0.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard
.
* generation atomic exit exception when in parallel environment.
* fixup a lot of concrete bugs.
V2
* use float16_compare{_quiet}
* only use GETPC() in outer most helper
* add ctx.ext_v Property
LIU Zhiwei (60):
target/riscv: add vector extension field in CPURISCVState
target/riscv
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 25
target/riscv/insn32.decode | 9 +++
target/riscv/insn_trans/trans_rvv.inc.c | 44 +
target/riscv/vector_helper.c| 82 +
4 files changed, 160
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 16
target/riscv/insn32.decode | 5 ++
target/riscv/insn_trans/trans_rvv.inc.c | 107
target/riscv/vector_helper.c| 89
4 files changed, 217
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 13
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 91 +
target/riscv/vector_helper.c| 14
4 files changed, 124 insertions(+)
diff
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 33 ++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c| 147
4 files changed, 198 insertions(+)
diff
101 - 200 of 1860 matches
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