On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.
Signed-off-by: Daniel Hen
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not updati
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 i
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
The setter is doing nothing special. Just set env->priv_ver directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is
used in all generic CPUs:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
When a new PRIV version is made available we can just
On 2023/3/9 15:27, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC
On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
By the way, do you know why mstatus_tvm and hstatus_tvm are needed?
The specification said,
The TVM mechanism improves
On 2023/3/10 17:08, CHEN Yi wrote:
-Original Messages-
*From:*"LIU Zhiwei"
*Sent Time:*2023-03-10 10:12:10 (Friday)
*To:* chenyi2...@zju.edu.cn, qemu-devel@nongnu.org
*Cc:* "Palmer Dabbelt" , "Alistair Francis"
, "Bin Meng&qu
On 2023/3/11 2:03, Alex Bennée wrote:
This replaces the previous attempt to add c-sky.com so I've dropped
the review/ack tags. Group everything under Alibaba now.
Added as requested by LIU Zhiwei.
Signed-off-by: Alex Bennée
Cc: LIU Zhiwei
Cc: Xuan Zhuo
Cc: Guo Ren
---
contrib/
k for XTHEAD*. I once sent a multiple disassemble path patch set for
custom extensions.
https://www.mail-archive.com/qemu-devel@nongnu.org/msg906222.html
We may continue this work based on that patch set.
Zhiwei
Co-developed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
disas/ri
Hi Richard,
When I read the tcg code, I find a corner case which may be a bug in
liveness_pass_1.
I see all TEMP_TBs or global temps are set to TS_DEAD | TS_MEM when
enter liveness_pass_1. Think about the sequence.
1)Write_global_temp_0 // 0->TS_DEAD, but not recorded in arg_life
2)INDEX
p(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
0);
+} else if (strstr(buffer, "mmu") != NULL) {
+assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+} else if (strstr(buffer, "uarch") != NULL) {
+assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+}
+}
+
+fclose(fp);
+return 0;
+}
Reviewed-by: LIU Zhiwei
Zhiwei
(env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT,
GETPC());
} else {
tlb_flush(cs);
@@ -403,7 +403,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
-if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT,
GETPC());
}
Reviewed-by: LIU Zhiwei
Zhiwei
On 2023/3/17 22:02, Richard Henderson wrote:
On 3/16/23 19:57, LIU Zhiwei wrote:
Hi Richard,
When I read the tcg code, I find a corner case which may be a bug in
liveness_pass_1.
I see all TEMP_TBs or global temps are set to TS_DEAD | TS_MEM when
enter liveness_pass_1. Think about the
-vext_version = VEXT_VERSION_1_00_0;
-} else {
-error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
-return;
-}
-} else {
-qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-}
-set_vext_version(env, vext_version);
Reviewed-by: LIU Zhiwei
Zhiwei
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
not specified, "
"use the default value v1.0\n");
}
-set_vext_version(env, vext_version);
+env->vext_ver = vext_version;
Reviewed-by: LIU Zhiwei
Zhiwei
}
/*
cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -1160,7 +1156,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (priv_version >= PRIV_VERSION_1_10_0) {
-set_priv_version(env, priv_ve
0,
+
+PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
Reviewed-by: LIU Zhiwei
Zhiwei
};
#define VEXT_VERSION_1_00_0 0x0001
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 8
1 file changed, 4 insertions(+), 4
patch, this patch looks good to me.
Reviewed-by: LIU Zhiwei
Zhiwei
A
better place to put this code is at the end of
riscv_cpu_validate_set_extensions() after all the validations are
completed.
Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the
extesions after the validati
TS_DEAD means we will release the register allocated for this temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bb52bc060b
On 2023/3/21 14:06, Richard Henderson wrote:
On 3/20/23 21:53, LIU Zhiwei wrote:
TS_DEAD means we will release the register allocated for this
temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
Test case?
I have run an Ubuntu image
On 2023/3/22 0:10, Richard Henderson wrote:
On 3/20/23 23:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called f
On 2023/3/22 10:47, Wu, Fei wrote:
On 3/22/2023 9:58 AM, LIU Zhiwei wrote:
On 2023/3/22 0:10, Richard Henderson wrote:
On 3/20/23 23:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited
On 2023/3/22 14:40, Wu, Fei wrote:
On 3/22/2023 11:36 AM, Wu, Fei wrote:
On 3/22/2023 11:31 AM, Richard Henderson wrote:
On 3/21/23 19:47, Wu, Fei wrote:
You should be making use of different softmmu indexes, similar to how
ARM uses a separate index for PAN (privileged access never) mode. I
;
-break;
-#endif
-case MXL_RV32:
-cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
-default:
-g_assert_not_reached();
-}
-assert(env->misa_mxl_max == env->misa_mxl);
-
Reviewed-by: LIU Zhiwei
Zhiwei
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
On 2023/3/23 6:19, Daniel Henrique Barboza wrote:
In the near future, write_misa() will use a variation of what we have
now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation
will be required in write_misa()
I don't know why pmp and epmp should be checked in write_misa().
As
static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
#ifndef CONFIG_USER_ONLY
+if (cpu->cfg.ext_sstc) {
+riscv_timer_init(cpu);
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
if (cpu->cfg.pmu_num) {
if (!riscv_pmu_init(cpu, cpu-&g
() */
+cpu->cfg.ext_ifencei = true;
+cpu->cfg.ext_icsr = true;
+cpu->cfg.pmp = true;
}
#endif
@@ -1384,11 +1425,6 @@ static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
-cpu->cfg.ext_ifencei = true;
-cpu->cfg.ext_icsr = true;
-cpu->cfg.mmu = true;
-cpu->cfg.pmp = true;
-
Reviewed-by: LIU Zhiwei
Zhiwei
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
sa(env, env->misa_mxl, ext);
+env->misa_ext_mask = env->misa_ext = ext;
Reviewed-by: LIU Zhiwei
Zhiwei
}
#ifndef CONFIG_USER_ONLY
On 2023/3/23 6:19, Daniel Henrique Barboza wrote:
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
obje
On 2023/3/23 10:14, LIU Zhiwei wrote:
On 2023/3/23 6:19, Daniel Henrique Barboza wrote:
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need
Hi Daniel,
I want to share my opinions about the cpu->cfg and misa.
Two suggestions:
1) The cpu->cfg should be set only once in cpu initialization
phrase(cpu_init_fn or cpu_realize_fn), and never changes any more in
other times(for example write_misa).
2) Set the misa only when cpu->cfg is
On 2023/3/23 10:44, Fei Wu wrote:
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx.
For patch set has more than 1 patch, usually add a cover letter.
Signed-off-by: Fei Wu
---
target/riscv/cpu.h
On 2023/3/23 14:00, Wu, Fei wrote:
On 3/23/2023 1:37 PM, LIU Zhiwei wrote:
On 2023/3/23 10:44, Fei Wu wrote:
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx.
For patch set has more than 1 patc
The guest should be able to set the vill bit as part of vsetvl.
Currently we may set env->vill to 1 in the vsetvl helper, but there
is nowhere that we set it to 0, so once it transitions to 1 it's stuck
there until the system is reset.
Signed-off-by: LIU Zhiwei
---
target/riscv/vector_
On 2022/2/1 10:12, Alistair Francis wrote:
On Sat, Jan 29, 2022 at 2:10 AM Peter Maydell wrote:
On Fri, 21 Jan 2022 at 09:42, Alistair Francis
wrote:
From: LIU Zhiwei
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
2:
https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren
Tested-by: Bin Meng
Reviewed-by: Liu Zhiwei
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/cpu_helper.c | 2 +-
2 files
On 2022/1/19 上午11:24, Alistair Francis wrote:
On Thu, Jan 13, 2022 at 9:50 PM LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
I'm not clear on why this is better?
Current xlen has been used in helper functions and many other places.
The computation of current xlen is not so trivia
ption
Use XL instead of OL in many places
Use pointer masking and XLEN for vector address
Define an common fuction to calculate address for ld
LIU Zhiwei (22):
target/riscv: Adjust pmpcfg access with mxl
target/riscv: Don't save pc when exception return
target/riscv: Sign extend li
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 19 +++
target/riscv/pmp.c | 12
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a9e7ac903b
load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 31 +++
target/riscv/cpu_helper.c | 34
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
target/riscv/translate.c| 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 8 ++---
target/riscv/gdbstub.c | 71 +++---
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 12
target/riscv/op_helper.c| 3 ++-
2 files changed, 10 insertions(+), 5
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
.../riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc | 5 ++--
target/riscv
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 32
1 file changed, 8 insertions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b11d92b51b..90f78eca65 100644
--- a/target/riscv
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 4
target/riscv/cpu_helper.c | 43 +++
target/riscv/csr.c| 19 +
target
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c| 3 +--
target/riscv/csr.c | 13 -
target/riscv/machine.c
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 9 +++--
target
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9be2820d2b..c00a82022e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/vector_helper.c | 7 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6c740b92c1
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 ++-
target
Signed-off-by: LIU Zhiwei
Acked-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe58ccaeae..55635d68d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,7
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 90f78eca65..c6b2407a06 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -584,7
On 2022/1/20 上午8:35, Alistair Francis wrote:
On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff
On 2022/1/20 上午8:35, Alistair Francis wrote:
On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei wrote:
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 17 -
1 file changed, 12 insertions(+), 5 deletions(-)
diff
Address Bits: 54
Boot HART MHPM Count : 0
Boot HART MIDELEG : 0x0666
Boot HART MEDELEG : 0x00f0b509
QEMU: Terminated
Thanks,
Zhiwei
On 2022/1/20 上午11:29, Alistair Francis wrote:
On Thu, Jan 20, 2022 at 12:12 PM LIU Zhiwei wrote:
On 2022/1/20 上午8:35, A
patch sequence
v2:
Split out vill from vtype
Remove context switch when xlen changes at exception
Use XL instead of OL in many places
Use pointer masking and XLEN for vector address
Define an common fuction to calculate address for ld
LIU Zhiwei (23):
target/riscv: Adjust pmpcfg access wit
load. So that we can only
recompute xlen in this places and cache it into CPURISCVState.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 31 +++
target/riscv/cpu_helper.c | 34
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9be2820d2b..c00a82022e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 12
target/riscv/op_helper.c| 3 ++-
2 files changed, 10 insertions(+), 5
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 19 +++
target/riscv/pmp.c | 12
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a9e7ac903b
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/cpu.c| 1 +
target/riscv/cpu.h| 4
target/riscv/cpu_helper.c | 43 +++
target/riscv/csr.c| 19 +
target
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
target/riscv/translate.c| 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 523d07a95e..e5f9d4ef93 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -584,7
Replace the array of pm_mask/pm_base with scalar variables.
Remove the cached array value in DisasContext.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 32
1 file changed, 8 insertions
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
.../riscv/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc | 5 ++--
target/riscv
Define one common function to compute a canonical address from a register
plus offset. Merge gen_pm_adjust_address into this function.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 9 +++--
target
We need not specially process vtype when XLEN changes.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c| 3 +--
target/riscv/csr.c | 13 -
target/riscv/machine.c
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 8 ++---
target/riscv/gdbstub.c | 71 +++---
2 files changed, 55 insertions(+), 24 deletions(-)
diff --git a/target/riscv/cpu.c b/target
Use cached cur_pmmask and cur_pmbase to infer the
current PM mode.
This may decrease the TCG IR by one when pm_enabled
is true and pm_base_enabled is false.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 3 ++-
target
The mask comes from the pointer masking extension, or the max value
corresponding to XLEN bits.
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 25 +++--
1 file changed, 15 insertions(+), 10 deletions
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 +
target/riscv/vector_helper.c | 7 +--
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6c740b92c1
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
Signed-off-by: LIU Zhiwei
Acked-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe58ccaeae..55635d68d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,7
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 28 ++--
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv
/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren
Tested-by: Bin Meng
Reviewed-by: Liu Zhiwei
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
target/riscv/cpu_bits.h | 7 +++
target/riscv/cpu_helper.c | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target
On 2022/1/21 上午9:50, Guo Ren wrote:
On Fri, Jan 21, 2022 at 6:48 AM LIU Zhiwei wrote:
On 2022/1/20 下午9:47, Guo Ren wrote:
Hi Alistair and Anup,
On Tue, Jan 18, 2022 at 12:56 PM Alistair Francis wrote:
On Tue, Jan 18, 2022 at 1:31 PM Anup Patel wrote:
On Tue, Jan 18, 2022 at 6:47 AM
On 2022/1/24 上午8:59, Alistair Francis wrote:
From: Alistair Francis
This series adds a MO_ op to specify that a load instruction should
produce a store fault. This is used on RISC-V to produce a store/amo
fault when an atomic access fails.
Hi Alistair,
As Richard said, we can address thi
gen_lr(ctx, a, (MO_ALIGN | MO_TESL));
Typo. This changes nothing.
Besides, I think we can add MO_WRITE_FAULT for SC in this patch or
another patch.
Otherwise,
Reviewed-by: LIU Zhiwei
Thanks,
Zhiwei
}
static bool trans_sc_w(DisasContext *ctx, arg_sc_w *a)
@@ -105,55 +105,64 @@ static
On 2022/1/24 下午3:49, Frédéric Pétrot wrote:
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, leading to the occurence of
"code should not be reached" in a few places.
This patch makes rv128 react as rv64 for gdb, as previously.
If
On 2022/1/25 04:24, Frédéric Pétrot wrote:
The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.
Signed-off-by: Frédéric Pétrot
Reviewed-by: LIU Zhiwei
System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf
Signed-off-by: Guo Ren
Cc: Liu Zhiwei
Cc: Bin Meng
Cc: Alistair Francis
---
target/riscv/cpu.h| 13 +
target/riscv/cpu_bits.h | 7
On 2022/1/25 16:40, Guo Ren wrote:
On Tue, Jan 25, 2022 at 4:34 PM LIU Zhiwei wrote:
On 2022/1/25 14:45, Weiwei Li wrote:
From: Guo Ren
Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we
need to ignore them. They cannot be a part of ppn.
1: The RISC-V Instruction Set
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7d0aee6769..eb425d74d2 100644
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei
---
target/riscv/translate.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
target/riscv/vector_he
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