[PATCH v7 39/61] target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 37 + target/riscv/insn32.decode | 12 ++ target/riscv/insn_trans/trans_rvv.inc.c | 35 + target/riscv/vector_helper.c| 174 4 files changed, 258 insertions

[PATCH v7 40/61] target/riscv: vector floating-point classify instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 33 + target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 3 + target/riscv/internals.h

[PATCH v7 41/61] target/riscv: vector floating-point merge instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 38 + target/riscv/vector_helper.c| 24 4 files changed, 68 insertions

[PATCH v7 42/61] target/riscv: vector floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33 + 4

[PATCH v7 43/61] target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 47 + target/riscv/vector_helper.c| 42

[PATCH v7 44/61] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 47 + target/riscv/vector_helper.c| 39

[PATCH v7 45/61] target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 74 + 4

[PATCH v7 46/61] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11 +++ 4 files changed, 24

[PATCH v7 47/61] target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 5 target/riscv/vector_helper.c| 39 + 4 files

[PATCH v7 48/61] target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 46 + 4 files changed

[PATCH v7 49/61] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 35 ++ target/riscv/vector_helper.c| 40

[PATCH v7 50/61] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4

[PATCH v7 51/61] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4

[PATCH v7 52/61] target/riscv: set-X-first mask bit

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 28 +++ target/riscv/vector_helper.c| 63 + 4

[PATCH v7 53/61] target/riscv: vector iota instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 27 +++ target/riscv/vector_helper.c| 29

[PATCH v7 57/61] target/riscv: floating-point scalar move instructions

Signed-off-by: LIU Zhiwei --- target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 54 + 2 files changed, 56 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0741a25540..79f9b37b29 100644 --- a

[PATCH v7 54/61] target/riscv: vector element index instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 25 + target/riscv/vector_helper.c| 24

[PATCH v7 55/61] target/riscv: integer extract instruction

Signed-off-by: LIU Zhiwei --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 116 2 files changed, 117 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1231628cb2..26dd0f1b1b 100644

[PATCH v7 58/61] target/riscv: vector slide instructions

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 target/riscv/vector_helper.c| 114 4 files

[PATCH v7 56/61] target/riscv: integer scalar move instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 60 + 2 files changed, 61 insertions(+) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index

[PATCH v7 59/61] target/riscv: vector register gather instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvv.inc.c | 77 + target/riscv/vector_helper.c| 60

[PATCH v7 60/61] target/riscv: vector compress instruction

Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 5 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 26

[PATCH v7 61/61] target/riscv: configure and turn on vector extension from command line

s, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. These properties can be specified with other values. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/

Re: [PATCH v4 5/5] target/riscv: add vector amo operations

On 2020/2/29 2:46, Richard Henderson wrote: On 2/28/20 1:19 AM, LIU Zhiwei wrote: +#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ETYPE, MTYPE, H, DO_OP, SUF)  \ +static void vext_##NAME##_noatomic_op(void *vs3, target_ulong addr,  \ +    uint32_t wd, uint32_t idx, CPURISCVState *env

[PATCH v6 3/4] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v6 2/4] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v6 1/4] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v6 0/4] target-riscv: support vector extension part 1

memory block for vector register description. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (4): target/riscv: add vector extension field in CPURISCVState target/riscv: implementation-defined constant parameters target/r

[PATCH v6 4/4] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makef

Re: [PATCH v4 2/5] target/riscv: add vector stride load and store instructions

On 2020/2/28 3:36, Richard Henderson wrote: On 2/25/20 2:35 AM, LIU Zhiwei wrote: +GEN_VEXT_LD_ELEM(vlsb_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_h, int8_t, int16_t, H2, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_w, int8_t, int32_t, H4, ldsb) +GEN_VEXT_LD_ELEM(vlsb_v_d, int8_t

Re: [PATCH v4 1/5] target/riscv: add vector unit stride load and store instructions

On 2020/2/28 3:17, Richard Henderson wrote: On 2/25/20 2:35 AM, LIU Zhiwei wrote: +static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen) +{ +int legal = widen ? 2 << s->lmul : 1 << s->lmul; + +return !((s->lmul == 0x3 && widen) || (reg

[PATCH v3 07/60] target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h

[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v3 00/60] target/riscv: support vector extension v0.7.1

. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (60): target/riscv: add vector extension field in CPURISCVState target/riscv

[PATCH v3 03/60] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v3 09/60] target/riscv: vector single-width integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 21 +++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 220 target/riscv/vector_helper.c| 122 + 4 files changed, 373 insertions

[PATCH v3 04/60] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makef

[PATCH v3 10/60] target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 target/riscv/insn32.decode | 16 +++ target/riscv/insn_trans/trans_rvv.inc.c | 154 target/riscv/vector_helper.c| 112 + 4 files changed, 331

[PATCH v3 02/60] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 88 + 4 files changed, 139 insertions

[PATCH v3 05/60] target/riscv: add vector stride load and store instructions

the base effective address. It can been seen as a special case of strided operations. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 6 + target/riscv/helper.h | 105 ++ target/riscv/insn32.decode | 32 ++ target/riscv/insn_trans

[PATCH v3 06/60] target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 35 +++ target/riscv/insn32.decode

[PATCH v3 24/60] target/riscv: vector single-width averaging add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvv.inc.c | 7 ++ target/riscv/vector_helper.c| 129 4 files changed, 158 insertions(+) diff

[PATCH v3 08/60] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h

[PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 +++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c| 103 4 files changed, 118 insertions(+) diff

[PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 16 + target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 7 target/riscv/vector_helper.c| 48 + 4 files changed, 76 insertions

[PATCH v3 12/60] target/riscv: vector bitwise logical instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 + target/riscv/insn_trans/trans_rvv.inc.c | 11 ++ target/riscv/vector_helper.c| 51 + 4 files changed, 96 insertions

[PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 109 4 files changed, 140 insertions(+) diff

[PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 10 + target/riscv/insn_trans/trans_rvv.inc.c | 16 ++ target/riscv/vector_helper.c| 278 4 files changed, 337 insertions(+) diff

[PATCH v3 18/60] target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74 + 4 files changed, 125 insertions

[PATCH v3 34/60] target/riscv: vector widening floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 + target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ target/riscv/vector_helper.c| 84 + 4 files changed, 119 insertions(+) diff

[PATCH v3 19/60] target/riscv: vector widening integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 + target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvv.inc.c | 8 target/riscv/vector_helper.c| 51 + 4 files changed, 84 insertions

[PATCH v3 40/60] target/riscv: vector floating-point merge instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 12 +++ target/riscv/vector_helper.c| 28 + 4 files changed, 45 insertions

[PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 10 ++ target/riscv/vector_helper.c| 147 4 files changed, 198 insertions(+) diff

[PATCH v3 39/60] target/riscv: vector floating-point classify instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 62 + 4 files changed, 70 insertions(+) diff --git a

[PATCH v3 13/60] target/riscv: vector single-width bit shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 25 target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvv.inc.c | 44 + target/riscv/vector_helper.c| 82 + 4 files changed, 160

[PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 16 target/riscv/insn32.decode | 5 ++ target/riscv/insn_trans/trans_rvv.inc.c | 107 target/riscv/vector_helper.c| 89 4 files changed, 217

[PATCH v3 14/60] target/riscv: vector narrowing integer right shift instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 91 + target/riscv/vector_helper.c| 14 4 files changed, 124 insertions(+) diff

[PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c| 180 4 files changed, 218 insertions(+) diff

[PATCH v3 42/60] target/riscv: widening floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 ++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 42 +++ target/riscv/vector_helper.c| 45 + 4 files changed, 103

[PATCH v3 21/60] target/riscv: vector widening integer multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 target/riscv/insn32.decode | 7 target/riscv/insn_trans/trans_rvv.inc.c | 9 + target/riscv/vector_helper.c| 45 + 4 files changed, 83 insertions

[PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11 +++ 4 files changed, 24 insertions(+) diff --git a/target

[PATCH v3 30/60] target/riscv: vector widening floating-point add/subtract instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 17 +++ target/riscv/insn32.decode | 8 ++ target/riscv/insn_trans/trans_rvv.inc.c | 131 target/riscv/vector_helper.c| 77 ++ 4 files changed, 233 insertions

[PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 128 4 files changed, 155 insertions(+) diff

[PATCH v3 22/60] target/riscv: vector integer merge and move instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 24 ++ target/riscv/vector_helper.c| 58 + 4 files changed, 94 insertions

[PATCH v3 15/60] target/riscv: vector integer comparison instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 57 +++ target/riscv/insn32.decode | 20 target/riscv/insn_trans/trans_rvv.inc.c | 66 target/riscv/vector_helper.c| 130 4 files changed, 273

[PATCH v3 38/60] target/riscv: vector floating-point compare instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 37 target/riscv/insn32.decode | 12 ++ target/riscv/insn_trans/trans_rvv.inc.c | 33 target/riscv/vector_helper.c| 221 4 files changed, 303 insertions(+) diff

[PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 ++ target/riscv/insn32.decode | 10 ++ target/riscv/insn_trans/trans_rvv.inc.c | 108 ++ target/riscv/vector_helper.c| 140 4 files changed, 291

[PATCH v3 48/60] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 28 + target/riscv/vector_helper.c| 40 + 4 files changed, 85

[PATCH v3 35/60] target/riscv: vector floating-point square-root instruction

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvv.inc.c | 37 +++ target/riscv/vector_helper.c| 40 + 4 files changed, 84

[PATCH v3 41/60] target/riscv: vector floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 ++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 6 + target/riscv/vector_helper.c| 33 + 4 files changed, 56 insertions

[PATCH v3 36/60] target/riscv: vector floating-point min/max instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 6 ++ target/riscv/vector_helper.c| 27 + 4 files changed, 50 insertions

[PATCH v3 43/60] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 42 + target/riscv/vector_helper.c| 42 + 4 files changed

[PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 + target/riscv/insn32.decode | 16 ++ target/riscv/insn_trans/trans_rvv.inc.c | 18 ++ target/riscv/vector_helper.c| 228 4 files changed, 311 insertions(+) diff

[PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 19 +++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 +++ target/riscv/vector_helper.c| 76 + 4 files changed, 109 insertions(+) diff

[PATCH v3 32/60] target/riscv: vector widening floating-point multiply

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 5 + target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 22 ++ 4 files changed, 33 insertions(+) diff --git

[PATCH v3 00/60] target/riscv: support vector extension v0.7.1

. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (60): target/riscv: add vector extension field in CPURISCVState target/riscv

[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v3 02/60] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v3 03/60] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v3 16/60] target/riscv: vector integer min/max instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 71 + 4 files changed, 122 insertions

[PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 7 +++ target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvv.inc.c | 4 target/riscv/vector_helper.c| 11 +++ 4 files changed, 24 insertions(+) diff --git a/target

[PATCH v3 44/60] target/riscv: vector single-width integer reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 17 ++ target/riscv/vector_helper.c| 76 + 4 files changed, 134 insertions

[PATCH v3 46/60] target/riscv: vector single-width floating-point reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 10 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvv.inc.c | 5 target/riscv/vector_helper.c| 39 + 4 files changed, 58 insertions(+) diff

[PATCH v3 48/60] target/riscv: vector mask-register logical instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 9 ++ target/riscv/insn32.decode | 8 + target/riscv/insn_trans/trans_rvv.inc.c | 28 + target/riscv/vector_helper.c| 40 + 4 files changed, 85

[PATCH v3 47/60] target/riscv: vector widening floating-point reduction instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c| 50 + 4 files changed, 58 insertions(+) diff --git a

[PATCH v3 49/60] target/riscv: vector mask population count vmpopc

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 20 4 files changed, 55 insertions

[PATCH v3 50/60] target/riscv: vmfirst find-first-set mask bit

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 2 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 32 + target/riscv/vector_helper.c| 19 +++ 4 files changed, 54 insertions

[PATCH v3 07/60] target/riscv: add fault-only-first unit stride load

The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h

[PATCH v3 03/60] target/riscv: support vector extension csr

The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 - 2 files

[PATCH v3 43/60] target/riscv: narrowing floating-point/integer type-convert instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 11 +++ target/riscv/insn32.decode | 5 +++ target/riscv/insn_trans/trans_rvv.inc.c | 42 + target/riscv/vector_helper.c| 42 + 4 files changed

[PATCH v3 04/60] target/riscv: add vector configure instruction

vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Signed-off-by: LIU Zhiwei --- target/riscv/Makef

[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState

The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard

[PATCH v3 18/60] target/riscv: vector integer divide instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 33 +++ target/riscv/insn32.decode | 8 +++ target/riscv/insn_trans/trans_rvv.inc.c | 10 target/riscv/vector_helper.c| 74 + 4 files changed, 125 insertions

[PATCH v3 02/60] target/riscv: implementation-defined constant parameters

vlen is the vector register length in bits. elen is the max element size in bits. vext_spec is the vector specification version, default value is v0.7.1. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 7 +++ target/riscv

[PATCH v3 10/60] target/riscv: vector widening integer add and subtract

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 49 target/riscv/insn32.decode | 16 +++ target/riscv/insn_trans/trans_rvv.inc.c | 154 target/riscv/vector_helper.c| 112 + 4 files changed, 331

[PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions

Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 13 +++ target/riscv/insn32.decode | 6 ++ target/riscv/insn_trans/trans_rvv.inc.c | 8 ++ target/riscv/vector_helper.c| 128 4 files changed, 155 insertions(+) diff

[PATCH v3 00/60] target/riscv: support vector extension v0.7.1

. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (60): target/riscv: add vector extension field in CPURISCVState target/riscv

[PATCH v3 06/60] target/riscv: add vector index load and store instructions

Vector indexed operations add the contents of each element of the vector offset operand specified by vs2 to the base effective address to give the effective address of each element. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 35 +++ target/riscv/insn32.decode

[PATCH v3 08/60] target/riscv: add vector amo operations

Vector AMOs operate as if aq and rl bits were zero on each element with regard to ordering relative to other instructions in the same hart. Vector AMOs provide no ordering guarantee between element operations in the same vector AMO instruction Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h

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