Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 67 +++
target-xtensa
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 95 +++
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 433e1ba..26cce83
inline GDB does not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c
Signed-off-by: Max Filippov
---
gdbstub.c | 96 +++
targ
es or uregnames are considered valid.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 47 +++-
2 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> I just had a very quick look and it Looks good to me too. Would be awesome
> if Max could provide something to test with in binary form. Maybe we could
> put it on the wiki's download page.
Tarball of my current kernel and rootfs is available at
http://jcmvbkbc.spb.ru/~dumb/ws/osll/qemu-xtensa/2
- mark privileged opcodes with ring check;
- make debug exception on exception handler entry.
Signed-off-by: Max Filippov
---
cpu-exec.c|6 +++
target-xtensa/cpu.h | 67
target-xtensa/helper.c| 37 +++-
target-xtensa
- TLB opcode group;
- region protection option (ISA, 4.6.3);
- region translation option (ISA, 4.6.4);
- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 56 -
target-xtensa/helper.c
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 53 -
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 29
3 files changed, 77 insertions(+), 6 deletions(-)
diff --git a/target-xtensa/cpu.h b
See ISA, 4.3.9
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 109 +++--
2 files changed, 86 insertions(+), 24 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 14d62fa..339075d
See ISA, 4.7.1.3 for details.
Window check is inserted before commands that push "used register
watermark" beyond its current level. Used register watermark is reset on
instructions that change WINDOW_BASE/WINDOW_START SRs.
Signed-off-by: Max Filippov
---
target-xtensa/translat
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 ++
target-xtensa/helper.c|1 +
target-xtensa/translate.c | 37 +
3 files
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 77 -
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dccd453..bc04a10 100644
--- a/target-xtensa/translate.c
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values that
correspond to default VECBASE value.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |2 ++
target-xtensa/helper.c| 18 --
target-xtensa/translate.c |1
Tensilica iss provides support for applications running in freestanding
environment through SIMCALL command. It is used by Tensilica libc to
access argc/argv, for file I/O, etc.
Note that simcalls that accept buffer addresses expect virtual addresses.
Signed-off-by: Max Filippov
All operations in this group are no-ops, because there are no delayed
side effects.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa
- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 164
es or uregnames are considered valid.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |7 ++
target-xtensa/translate.c | 49 +++-
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
See ISA, 4.4.4 for details.
Correct (aligned as per ISA) address for unaligned access is generated
in case this option is not enabled.
Signed-off-by: Max Filippov
---
target-xtensa/helper.c|4 ++-
target-xtensa/op_helper.c | 26
target-xtensa/translate.c
Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 67 +++
target-xtensa
All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 95 +++
Add myself as target-xtensa and DC232B maintainer.
Signed-off-by: Max Filippov
---
MAINTAINERS | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 508ea1e..72b2099 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -115,6 +115,12 @@ M
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4dfca2b..92547d2 100644
--- a/target
Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 110 -
1 files changed, 109 insertions
- ST1: SAR (shift amount special register) manipulation, NSA(U);
- RST1: shifts, 16-bit multiplication.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |4 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 14 +++
target-xtensa/translate.c | 242
Signed-off-by: Max Filippov
---
Makefile.target |2 +
arch_init.c |2 +
arch_init.h |1 +
cpu-exec.c|2 +
elf.h |2 +
hw/xtensa_pic.c | 38 ++
target-xtensa/cpu.h
- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/translate.c | 89 +
2
Group SNM0 (indirect jumps and calls).
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 9e26a65..78fffc5
- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 161 +
1 files
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 54 +
1 files changed, 54 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xte
looping code verifies actual LEND value.
Invalidation may be avoided for the TB at the new LEND address if
there's a way to associate LEND address with TB at compilation time and
later verify that it doesn't change.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |3 ++
tar
Sample board and sample CPU core are used for debug and may be used for
development of custom SoC emulators.
This board has two fixed size memory regions for DTCM and ITCM and
variable length SRAM region.
Signed-off-by: Max Filippov
---
Makefile.target|1 +
hw/xtensa_sample.c | 106
inline GDB does not support operations with privileged SRs
(see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support
may be enabled, see NUM_CORE_REGS comment in the gdbstub.c
Signed-off-by: Max Filippov
---
gdbstub.c | 96 +++
targ
Signed-off-by: Max Filippov
---
configure| 12 +++-
default-configs/xtensa-softmmu.mak |1 +
default-configs/xtensaeb-softmmu.mak |1 +
3 files changed, 13 insertions(+), 1 deletions(-)
create mode 100644 default-configs/xtensa-softmmu.mak
create
res, comparison order, missing braces);
- turn WINDOWBASE_BOUND and WINDOWSTART_BIT macros into inline functions;
- convert sample boards to memory API.
Git tree is available at git://jcmvbkbc.spb.ru/dumb/qemu-xtensa.git xtensa
Max Filippov (33):
target-xtensa: add target stubs
target-xtensa: add tar
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov
---
hw/xtensa_pic.c | 96
target-xtensa/cpu.h | 45 +-
target-xtensa/helper.c
This is Diamond 232L Standard Core Rev.B (LE).
Signed-off-by: Max Filippov
---
Makefile.target |1 +
hw/xtensa_dc232b.c| 116
target-xtensa/gdb-config-dc232b.c | 261 +
target-xtensa/helper.c
Signed-off-by: Max Filippov
---
hw/xtensa_sample.c|1 +
target-xtensa/cpu.h |2 ++
target-xtensa/translate.c |7 +++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 0aeb7c8..31a6f70 100644
--- a/hw
separate patch.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |8 ++
target-xtensa/helper.c|1 +
target-xtensa/helpers.h |8 ++
target-xtensa/op_helper.c | 192 +
target-xtensa/translate.c | 145
> > This series adds support for Tensilica Xtensa target.
> > Port status: Linux for DC232B works in the qemu.
> >Not implemented xtensa options: MAC16,
> >floating point coprocessor, cache option, debug option.
> >
> > v4 -> v5 changes:
> > - implement boolean option;
> > - fix v4 stylist
> > Tarball of my current kernel and rootfs is available at
> > http://jcmvbkbc.spb.ru/~dumb/ws/osll/qemu-xtensa/20110829/xtensa-dc232b_kernel_rootfs.tgz
> >
> > I can also publish unit tests binaries.
>
> Hi Max,
>
> Unit tests would be good too, but it would also be helpful if you could put
>
;
> To significant that you are able and willing to relicense your changes
> to the SoftFloat-1a license (or a GPL compatible license).
Acked-by: Max Filippov
--
Thanks.
-- Max
On Tue, May 14, 2013 at 12:04 AM, Anthony Green wrote:
> Fix a simple bug in tlb_fill for moxie. The port was mostly working
> before, which is why I only really noticed it recently. Thanks to
> @jcmvbkbc for tracking it down.
>
> Signed-off-by: Anthony Green
> ---
> target-moxie/helper.c | 2
Hi,
On Thu, Feb 13, 2014 at 11:34 AM, Alexey Kardashevskiy wrote:
> Hi!
>
> I am debugging spapr-vlan and hit the following issue.
>
> When I run QEMU as below, the kernel's DHCP client does not continue till I
> hit any key in console. If I replace spapr-vlan with
> e1000/rtl8139/virtio-net, eve
On Thu, Feb 13, 2014 at 2:34 PM, Alexey Kardashevskiy wrote:
> On 02/13/2014 07:40 PM, Max Filippov wrote:
>> Hi,
>>
>> On Thu, Feb 13, 2014 at 11:34 AM, Alexey Kardashevskiy
>> wrote:
>>> Hi!
>>>
>>> I am debugging spapr-vlan and hit the
On Thu, Feb 13, 2014 at 5:42 PM, Alexey Kardashevskiy wrote:
> On 02/13/2014 11:23 PM, Max Filippov wrote:
>> On Thu, Feb 13, 2014 at 2:34 PM, Alexey Kardashevskiy wrote:
>>> On 02/13/2014 07:40 PM, Max Filippov wrote:
>>>> Hi,
>>>>
>>>>
On Thu, Feb 13, 2014 at 6:06 PM, Alexey Kardashevskiy wrote:
> On 02/14/2014 01:02 AM, Max Filippov wrote:
>> On Thu, Feb 13, 2014 at 5:42 PM, Alexey Kardashevskiy wrote:
>>> On 02/13/2014 11:23 PM, Max Filippov wrote:
>>>> On Thu, Feb 13, 2014 at 2:34 PM, Ale
Hello,
this series collapses standard core configuration statements into a single
macro and adds support for two new special registers.
Max Filippov (2):
target-xtensa: refactor standard core configuration
target-xtensa: provide HW confg ID registers
target-xtensa/core-dc232b.c | 8
Signed-off-by: Max Filippov
---
target-xtensa/cpu.c | 2 ++
target-xtensa/cpu.h | 4
target-xtensa/overlay_tool.h | 9 -
target-xtensa/translate.c| 9 +++--
4 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/target-xtensa/cpu.c b/target-xtensa
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov
---
target-xtensa/core-dc232b.c | 8 +---
target-xtensa/core-dc233c.c | 8 +---
target-xtensa
ck2.h and
> which no longer get it indirectly have to be fixed. Use qemu/sockets.h
> to get winsock2.h. Add comments to all those new include statements.
>
> The modification in ui/vnc-enc-tight.c is needed temporarily and will be
> removed again in the following patch.
>
>
registers.
--------
Max Filippov (10):
hw/xtensa: add support for ML605 and KC705 FPGA board
opencores_eth: flush queue whenever can_receive can go from false to true
target-xtensa: add RRRI4 opcode format fields
target-xtensa: add basic checks to dcac
Hi Xin,
On Thu, Jan 23, 2014 at 11:49 PM, Xin Tong wrote:
[...]
> diff --git a/cputlb.c b/cputlb.c
> index b533f3f..03a048a 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -34,6 +34,22 @@
> /* statistics */
> int tlb_flush_count;
>
> +/* swap the 2 given TLB entries as well as their correspondi
On Fri, Jan 24, 2014 at 1:29 AM, Xin Tong wrote:
>>> +/* swap the 2 given TLB entries as well as their corresponding IOTLB */
>>> +inline void swap_tlb(CPUTLBEntry *te, CPUTLBEntry *se, hwaddr *iote,
>>> + hwaddr *iose)
>>> +{
>>> + hwaddr iotmp;
>>> + CPUTLBEntry t;
>>> +
Hello,
is there any way to notify networking core that adapter's
NetClientInfo::can_receive return value is about to change from 0 to 1?
I'm trying to talk to DHCP server from the recent (2014.01) u-boot running
in the xtensa system emulation over the tap interface. On the guest I see
the followin
Signed-off-by: Max Filippov
---
hw/xtensa/xtensa_lx60.c | 51 +
1 file changed, 47 insertions(+), 4 deletions(-)
diff --git a/hw/xtensa/xtensa_lx60.c b/hw/xtensa/xtensa_lx60.c
index 22e124d..49c58d1 100644
--- a/hw/xtensa/xtensa_lx60.c
+++ b/hw
On Sun, Feb 2, 2014 at 1:50 PM, Paolo Bonzini wrote:
> Il 02/02/2014 02:47, Max Filippov ha scritto:
>
>> Hello,
>>
>> is there any way to notify networking core that adapter's
>> NetClientInfo::can_receive return value is about to change from 0 to 1?
>
>
arrives but the
current RX descriptor is not empty.
Signed-off-by: Max Filippov
---
hw/net/opencores_eth.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c
index 4118d54..4a44304 100644
--- a/hw
This encoding is used by cache instructions.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dc5e78f..b0b7fa0 100644
--- a/target-xtensa/translate.c
+++ b/target
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.
Signed-off-by: Max Filippov
---
target-xtensa
Hello,
this series adds basic checks (privilege level, address validity, windowed
register validation) to all cache opcodes. This improves emulation quality
and allows to debug cache-related issues that happen on real hardware.
Max Filippov (6):
target-xtensa: add RRRI4 opcode format fields
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/macros.inc | 4
tests/tcg/xtensa/test_mmu.S | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.
Signed-off-by: Max Filippov
---
target-xtensa/helper.h
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile | 11 +++
tests/tcg/xtensa/macros.inc | 2 ++
tests/tcg/xtensa/test_b.S
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile | 1 +
tests/tcg/xtensa/test_cache.S | 97 +++
2 fi
On Tue, Feb 11, 2014 at 6:35 PM, Samuel Thibault
wrote:
> Eric Blake, le Tue 11 Feb 2014 06:50:54 -0700, a écrit :
>> On 02/11/2014 06:08 AM, Samuel Thibault wrote:
>> > This is a respin of IPv6 in Qemu -net user mode.
>>
>> When sending a new revision of a long series, it's easier if it appears
>
On Tue, Feb 11, 2014 at 6:42 PM, Max Filippov wrote:
> On Tue, Feb 11, 2014 at 6:35 PM, Samuel Thibault
> wrote:
>> Eric Blake, le Tue 11 Feb 2014 06:50:54 -0700, a écrit :
>>> On 02/11/2014 06:08 AM, Samuel Thibault wrote:
>>> > This is a respin of IPv6 in
On Mon, Oct 28, 2013 at 4:43 AM, Max Filippov wrote:
> This fixes qemu abort with the following message:
>
> include/qemu/int128.h:22: int128_get64: Assertion `!a.hi' failed.
>
> which happens due to attempt to invalidate breakpoint by virtual address
> for which get_p
pping.
----
Max Filippov (2):
exec: fix breakpoint_invalidate when pc may not be translated
target-xtensa: add missing DEBUG section to dc233c config
exec.c | 6 --
target-xtensa/core-dc233c.c | 1 +
2
On Mon, Nov 11, 2013 at 8:50 PM, Eric Blake wrote:
> Quick - identify the bug in this code (from ui/curses.c):
>
> static void curses_winch_handler(int signum)
> {
> struct winsize {
> unsigned short ws_row;
> unsigned short ws_col;
> unsigned short ws_xpixel; /* unus
On Wed, Nov 13, 2013 at 11:26 AM, Fardin wrote:
> Hi everyone,
>
> My question might look very stupid but the answer would really help me.
>
> I am working on Android emulator which is using QEMU. I need to print out
> the value of env->cp15.c13_fcse everytime the void tlb_flush(CPUState *env,
> i
oid
> emulator only for ARM.
You can add
#include "elf.h"
into cputlb.c and then decide based on ELF_MACHINE symbol, like
#if ELF_MACHINE == EM_ARM
> On Wed, Nov 13, 2013 at 1:59 AM, Max Filippov wrote:
>>
>> On Wed, Nov 13, 2013 at 11:26 AM, Fardin wrote:
>>
Hi Varad,
On Mon, Nov 18, 2013 at 5:49 PM, Varad Gautam wrote:
>
> Hi! I'm new here, and am working on my first bug. I have posted a patch
> for Bug#603872 [1]. It's incomplete right now, but please have a look and
> tell me if I'm headed in the right direction. (I don't know if I can send
> inco
On Fri, Apr 18, 2014 at 12:48 PM, Pavel Dovgaluk
wrote:
> You can insert tracing code into the functions from the
> “include\exec\softmmu_template.h” file: like helper_le_ld_name,
> helper_le_st_name and so on.
It's not enough, you also need to disable memory access fast path so that
these functi
17:23:46 +0400)
xtensa queue 2013-10-15
--------
Max Filippov (1):
target-xtensa: add in_asm logging
target-xtensa/translate.c | 8
1 file changed, 8 insertions(+)
--
1.8.1.4
On Fri, Sep 27, 2013 at 11:36 PM, Paolo Bonzini wrote:
> Il 27/09/2013 20:29, Max Filippov ha scritto:
>> Hi,
>>
>> I'm getting said assertion failure debugging linux userspace
>> application through the qemu gdbstub. The backtrace looks like this:
>>
>&g
This fixes missing debug feature opcodes of dc233c core variant.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
---
target-xtensa/core-dc233c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-xtensa/core-dc233c.c b/target-xtensa/core-dc233c.c
index 11acbf3..738d543 100644
On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke wrote:
> Hi Alex,
>
> I am using a cross-compiling toolchain. It's the easiest way as I have to
> compile the image for QEMU anyhow.
> http://opencores.org/or1k/OpenRISC_GNU_tool_chain
>
> Then it's just an "make && make test" in the corresponding
>
On Tue, Oct 22, 2013 at 8:15 PM, Sebastian Macke wrote:
> On 22/10/2013 9:01 AM, Max Filippov wrote:
>>
>> On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke
>> wrote:
>>>
>>> Hi Alex,
>>>
>>> I am using a cross-compiling toolchain. It'
nongnu.org/archive/html/qemu-devel/2013-09/msg04582.html
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
---
exec.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 2e31ffc..9150430 100644
--- a/exec.c
+++ b/exec.c
@@ -409,8 +409,10 @@ s
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
> This patch separates the load and store instruction to a
> separate function.
> The repetition of the source code can be reduced and further
> optimizations can be implemented.
> In this case it checks for a zero offset and optimizes it.
>
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
> At the moment there are two TLBs. The OpenRISC TLB followed
> by the QEMU's own TLB.
> At the end of the TLB miss handler a tlb_flush of QEMUs TLB
> is executed which is exactly what we want to avoid.
> As long as there is no context switc
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
> Hi,
>
> This is the second part of the patches to make the openrisc target faster
> and more reliable.
Hi Sebastian,
this series doesn't apply cleanly to the current qemu git head,
what tree is it based on?
--
Thanks.
-- Max
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
> srf is a boolean variable.
> Therefore the instruction should check for != 0 and not for != SR_F
>
> Signed-off-by: Sebastian Macke
> ---
> target-openrisc/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --gi
On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke wrote:
> Instead of testing the overflow exception dynamically every time
> The flag will be reckognized by the tcg as changed code and
> will recompile the code with the correct checks.
>
> Signed-off-by: Sebastian Macke
> ---
> target-openrisc/
On Wed, Oct 30, 2013 at 1:53 AM, Sebastian Macke wrote:
> On 29/10/2013 2:01 PM, Max Filippov wrote:
>>
>> On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke
>> wrote:
>>>
>>> At the moment there are two TLBs. The OpenRISC TLB followed
>>> by th
On Wed, Oct 30, 2013 at 1:36 AM, Sebastian Macke wrote:
> On 29/10/2013 1:05 PM, Max Filippov wrote:
>>
>> On Tue, Oct 29, 2013 at 11:04 PM, Sebastian Macke
>> wrote:
>>> Additional this patch solves a severe bug for the softmmu emulation.
>>> The pc ha
Hi Andreas,
On Mon, Mar 10, 2014 at 4:15 AM, Andreas Färber wrote:
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 4265378..8641e5d 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -54,7 +54,7 @@ static void do_unaligned_access(CPUXtensa
On Mon, Mar 10, 2014 at 4:15 AM, Andreas Färber wrote:
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 624ef54..612d3bf 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -730,21 +730,24 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState
On Mon, Feb 16, 2015 at 5:44 PM, Chen Gang S wrote:
> I guess, for qemu, we need !DISASM_ONLY, and may need BFD_RELOC, and may
> need the latest decode_X1_fsm, and also may need !__KERNEL__ -- which
> means we will use the full binutils version disassembler!!
Disassembler is not a crucial part of
ML605 daughterboard has 16MB flash, not 32MB. Change board definition
accordingly.
Signed-off-by: Max Filippov
---
hw/xtensa/xtfpga.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c
index e8793af..63a5291 100644
--- a/hw/xtensa
On Wed, Feb 18, 2015 at 5:10 PM, Vladimir Sementsov-Ogievskiy
wrote:
> On 18.02.2015 17:01, Eric Blake wrote:
>> On 02/18/2015 01:10 AM, Vladimir Sementsov-Ogievskiy wrote:
>>> Can anybody explain what the reasons, politics and consequences of
>>> adding RFC into patch header in this mailing list?
On Tue, Feb 3, 2015 at 8:28 AM, Kaiyuan wrote:
> Hello, guys
>
> I am trying to use gdb to debug qemu-system-ppc to see the details of tcg.
> However, after setting breakpoint in
> translate.c:gen_intermediate_code_internal and steps over, gdb showed
> message:
>
> Program received signal SIGUSR1,
On Wed, Mar 25, 2015 at 1:26 AM, Andreas Färber wrote:
> Am 24.03.2015 um 00:36 schrieb Alexander von Gluck IV:
>>
>> diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
>> index 16e9d8c..d0ea12a 100644
>> --- a/target-xtensa/xtensa-semi.c
>> +++ b/target-xtensa/xtensa-semi.c
>>
On Wed, Mar 25, 2015 at 2:03 AM, François Revol wrote:
> On 24/03/2015 23:56, Max Filippov wrote:
>> On Wed, Mar 25, 2015 at 1:26 AM, Andreas Färber wrote:
>>> Am 24.03.2015 um 00:36 schrieb Alexander von Gluck IV:
>>>>
>>>
>>> Why convert from
type, free after use.
>
> Cc: Michael Tokarev
> Cc: Edgar E. Iglesias
> Signed-off-by: Gonglei
> ---
> v2: fix a complier error.
> ---
> hw/microblaze/boot.c | 13 +++--
> 1 file changed, 7 insertions(+), 6 deletions(-)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
Hi,
this series implements do_unassigned_access callback for target-xtensa and
adds default memory access handler for the system I/O region of the XTFPGA
board to retain current behaviour.
Max Filippov (2):
hw/xtensa: allow reads/writes in the system I/O region
target-xtensa: implement
Ignore writes to unassigned areas of system I/O regison and return 0 for
reads. This makes drivers for unimportant unimplemented hardware blocks
happy.
Signed-off-by: Max Filippov
---
hw/xtensa/xtfpga.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw
Depending on access type raise either InstrPIFDataError or
LoadStorePIFDataError exception.
Signed-off-by: Max Filippov
---
target-xtensa/cpu-qom.h | 3 +++
target-xtensa/cpu.c | 1 +
target-xtensa/op_helper.c | 14 ++
3 files changed, 18 insertions(+)
diff --git a/target
when a sequence of entry opcodes is used for register
window spilling there may not be a call or other opcode that would cause
window check between entries and they would not raise overflow exception
themselves resulting in data corruption.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
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