[PATCH v38 18/22] target/avr: Add machine none test

Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- tests/machine-none-test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 5953d31755..3e5c74e73e 100644 --- a/tests/machine-none

[PATCH v38 15/22] target/avr: Add example board configuration

--git a/hw/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..6574733b57 --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,293 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redistribute it and/or + * modify it under th

[PATCH v38 08/22] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 243 + 1 file changed, 243 insertions(+) diff --git a/target/avr/translate.c b/target/avr

Re: [PATCH v38 00/22] QEMU AVR 8 bit cores

I hope I did not miss anything. On Sun, Dec 8, 2019 at 8:39 PM Michael Rolnik wrote: > This series of patches adds 8bit AVR cores to QEMU. > All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully > tested yet. > However I was able to execute simple code with fu

[PATCH v38 20/22] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --g

[PATCH v38 17/22] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 6 ++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ 4 files

[PATCH v38 07/22] target/avr: Add instruction translation - Data Transfer Instructions

This includes: - MOV, MOVW - LDI, LDS LDX LDY LDZ - LDDY, LDDZ - STS, STX STY STZ - STDY, STDZ - LPM, LPMX - ELPM, ELPMX - SPM, SPMX - IN, OUT - PUSH, POP - XCH - LAS, LAC LAT Signed-off-by: Michael Rolnik --- target/avr/translate.c | 861

[PATCH v38 22/22] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 21 + 1 file changed, 21 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..9ab7ed0865 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,27 @@ S

[PATCH v38 21/22] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé

[PATCH v38 16/22] target/avr: Add section about AVR into QEMU documentation

Signed-off-by: Michael Rolnik --- qemu-doc.texi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/qemu-doc.texi b/qemu-doc.texi index 3ddf5c0a68..cea1008800 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1757,6 +1757,7 @@ differences are mentioned in the following sections

[PATCH v38 19/22] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

[PATCH v38 13/22] target/avr: Add limited support for 16 bit timer peripheral

These were designed to facilitate testing but should provide enough function to be useful in other contexts. Only a subset of the functions of each peripheral is implemented, mainly due to the lack of a standard way to handle electrical connections (like GPIO pins). Signed-off-by: Sarah Harris

Re: [PATCH v38 18/22] target/avr: Add machine none test

:) no idea. all other machines / CPUs have it, so I added as well On Mon, Dec 9, 2019 at 8:13 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Sunday, December 8, 2019, Michael Rolnik wrote: > >> Signed-off-by: Michael Rolnik >> Tes

Re: [PATCH v38 15/22] target/avr: Add example board configuration

Yes, I did compile other platforms. On Mon, Dec 9, 2019 at 8:24 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Sunday, December 8, 2019, Michael Rolnik wrote: > >> A simple board setup that configures an AVR CPU to run a given firmware >>

Re: [PATCH v38 17/22] target/avr: Register AVR support with the rest of QEMU

I prefer to remove it, as nobody uses it. what do you think? the full list is in target/avr/cpu.h file On Mon, Dec 9, 2019 at 8:16 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Sunday, December 8, 2019, Michael Rolnik wrote: > >> Add AVR relat

Re: [PATCH v38 15/22] target/avr: Add example board configuration

I will check again. On Mon, Dec 9, 2019 at 8:30 PM Michael Rolnik wrote: > Yes, I did compile other platforms. > > On Mon, Dec 9, 2019 at 8:24 PM Aleksandar Markovic < > aleksandar.m.m...@gmail.com> wrote: > >> >> >> On Sunday, December 8, 2019, Micha

Re: [PATCH v38 11/22] target/avr: Add instruction disassembly function

Hi Aleksandar. 1. all instructions are 16 bit long except CALL & JMP they are 32 bit long 2. next_word_used is set to true by next_word when called by append_16 when CALL & JMP are parsed Regards, Michael Rolnik On Mon, Dec 9, 2019 at 8:10 PM Aleksandar Markovic < aleksandar.m.m..

Re: [PATCH v38 11/22] target/avr: Add instruction disassembly function

You are right. See at the bottom of the file. There is a comment about it Sent from my cell phone, please ignore typos On Tue, Dec 10, 2019, 6:21 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Monday, December 9, 2019, Michael Rolnik wrote: > >>

Re: [PATCH v38 11/22] target/avr: Add instruction disassembly function

Rolnik On Thu, Dec 12, 2019 at 11:12 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Tue, Dec 10, 2019 at 8:18 AM Michael Rolnik wrote: > > > > You are right. See at the bottom of the file. There is a comment about it > > > > Sorry, what file? &g

Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

On Thu, Nov 21, 2019 at 8:55 PM Philippe Mathieu-Daudé wrote: > > Hi Michael, > > On 10/29/19 10:24 PM, Michael Rolnik wrote: > > This includes: > > - CPU data structures > > - object model classes and functions > > - migration functions > > - GDB hoo

Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

It seems to be a huge investment. this function should parse the binary data as `decode_insn` does, so I suggest to modify decodetree tool to make decoding information available to the instruction print function. what do you think? On Thu, Nov 21, 2019 at 9:44 PM Michael Rolnik wrote: > >

Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

chard Henderson > > mailto:richard.hender...@linaro.org>> > wrote: > > > > On 11/21/19 8:53 PM, Michael Rolnik wrote: > > > It seems to be a huge investment. this function should parse the > > > binary data as `decode_insn` does, so I suggest to modi

Re: [PATCH v35 10/13] target/avr: Add limited support for USART and 16 bit timer peripherals

Sarah, could you please answer this question? Thanks, Michael On Fri, Nov 22, 2019 at 6:49 PM Aleksandar Markovic wrote: > > On Tue, Oct 29, 2019 at 10:25 PM Michael Rolnik wrote: > > > > From: Sarah Harris > > > > These were designed to facilitate tes

Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

+/* Set the number of interrupts supported by the CPU. */ > > +qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 57); > > +#endif > > Can you please, Michael, explain to me the origin of number "57" here? > > Thanks, Aleksandar -- Best Regards, Michael Rolnik

Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

gt; > +.parent = TYPE_CPU, > > +.instance_size = sizeof(AVRCPU), > > +.instance_init = avr_cpu_initfn, > > +.class_size = sizeof(AVRCPUClass), > > +.class_init = avr_cpu_class_init, > > + .abstract = true, > > +}, > > +DEFINE_AVR_CPU_TYPE("avr1", avr_avr1_initfn), > > +DEFINE_AVR_CPU_TYPE("avr2", avr_avr2_initfn), > > +DEFINE_AVR_CPU_TYPE("avr25", avr_avr25_initfn), > > +DEFINE_AVR_CPU_TYPE("avr3", avr_avr3_initfn), > > +DEFINE_AVR_CPU_TYPE("avr31", avr_avr31_initfn), > > +DEFINE_AVR_CPU_TYPE("avr35", avr_avr35_initfn), > > +DEFINE_AVR_CPU_TYPE("avr4", avr_avr4_initfn), > > +DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), > > +DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), > > +DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), > > +DEFINE_AVR_CPU_TYPE("xmega2", avr_xmega2_initfn), > > +DEFINE_AVR_CPU_TYPE("xmega4", avr_xmega4_initfn), > > +DEFINE_AVR_CPU_TYPE("xmega5", avr_xmega5_initfn), > > +DEFINE_AVR_CPU_TYPE("xmega6", avr_xmega6_initfn), > > +DEFINE_AVR_CPU_TYPE("xmega7", avr_xmega7_initfn), > > +}; > > + > > Hi, Michael, > > I have the hardest time finding in the documentation some kind of > table of AVR CPUs containing supported features. Related to that: > > - Is there a list in the docs equivalent to the definitions of > AVR_FEATURE_XXX constants in your code? > - How did you collect all info needed for definition of 15 CPUs above > (link to the source of info would be great)? > - Would all 15 CPUs be supported in QEMU once this series is > integrated, without caveats? > > Sincerely yours, > Aleksandar Hi Alexandar. you can find this info in different source 1. this wiki https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set 2. download all the speck and compare 3. GCC 1. https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html 2. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-mcus.def 3. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-arch.h 4. https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c as for the flags 1. AVR_FEATURE_SRAM defined but never used 2. AVR_FEATURE_LPM assigned for all cores, however there are more cores that do not support this instruction, so if added to QEMU will not have it defined for them. -- Best Regards, Michael Rolnik

[PATCH v36 00/17] QEMU AVR 8 bit cores

; 2. "target/avr: Update build system" 3. "target/avr: Update MAINTAINERS file" 4. split "target/avr: Add tests" patch into two patches 1. "target/avr: Add Avocado test" 2. "target/avr: Add boot serial test" 5. Add instruction disa

[PATCH v36 01/17] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov

[PATCH v36 07/17] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 1123 1 file changed, 1123 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v36 04/17] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik --- target/avr/translate.c | 132 + 1 file changed, 132 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr/translate.c new file mode 100644 index 00..53c9892a60

[PATCH v36 03/17] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/insn.decode | 175 + 1 file changed, 175 insertions(+) create mode 100644 target

[PATCH v36 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik --- target/avr/translate.c | 822 + 1 file changed, 822 insertions

[PATCH v36 13/17] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 6 ++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ tests

[PATCH v36 10/17] target/avr: Add instruction disassembly function

Provide function disassembles executed instruction when `-d in_asm` is provided Signed-off-by: Michael Rolnik --- target/avr/cpu.h | 1 + target/avr/cpu.c | 2 +- target/avr/disas.c | 214 + target/avr/translate.c | 11 +++ 4 files

[PATCH v36 02/17] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 354 2 files changed, 383

[PATCH v36 14/17] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

[PATCH v36 11/17] target/avr: Add limited support for USART and 16 bit timer peripherals

include/hw/misc/avr_mask.h new file mode 100644 index 00..d3e21972d8 --- /dev/null +++ b/include/hw/misc/avr_mask.h @@ -0,0 +1,47 @@ +/* + * AVR Power Reduction + * + * Copyright (c) 2019 Michael Rolnik + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software

[PATCH v36 16/17] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé

[PATCH v36 06/17] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik --- target/avr/translate.c | 549 - 1 file changed, 546

[PATCH v36 15/17] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --g

[PATCH v36 08/17] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 174 + 1 file changed, 174 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index f2ec2e2d2f..30ba13bdd7

[PATCH v36 09/17] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v36 12/17] target/avr: Add example board configuration

ode 100644 hw/avr/Makefile.objs diff --git a/hw/avr/sample.c b/hw/avr/sample.c new file mode 100644 index 00..2295ec1b79 --- /dev/null +++ b/hw/avr/sample.c @@ -0,0 +1,282 @@ +/* + * QEMU AVR CPU + * + * Copyright (c) 2019 Michael Rolnik + * + * This library is free software; you can redis

[PATCH v36 17/17] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..ad2d9dd04a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,15 @@ S: Maintained F: hw/arm

Re: [PATCH v36 17/17] target/avr: Update MAINTAINERS file

Aleksandar, there was an email from Sarah, stating that she does not want to be a maintainer. On Tue, Nov 26, 2019 at 5:17 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Sunday, November 24, 2019, Michael Rolnik wrote: > >> Include AVR mainta

Re: [PATCH v36 10/17] target/avr: Add instruction disassembly function

On Tue, Nov 26, 2019 at 9:52 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Sun, Nov 24, 2019 at 6:03 AM Michael Rolnik wrote: > > > > Provide function disassembles executed instruction when `-d in_asm` is > > provided > > > > Signed-off-

Re: [PATCH v36 04/17] target/avr: Add instruction translation - Registers definition

On Tue, Nov 26, 2019 at 9:48 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Sun, Nov 24, 2019 at 6:03 AM Michael Rolnik wrote: > > > > Signed-off-by: Michael Rolnik > > --- > > target/avr/translate.c | 132 +

Re: [PATCH v36 17/17] target/avr: Update MAINTAINERS file

Ah. I think Sarah was ok with reviewer role. On Tue, Nov 26, 2019 at 9:39 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Tue, Nov 26, 2019 at 8:06 PM Michael Rolnik wrote: > > > > Aleksandar, > > > > there was an email from Sarah, stati

Re: [PATCH v36 10/17] target/avr: Add instruction disassembly function

On Wed, Nov 27, 2019 at 1:59 AM Philippe Mathieu-Daudé wrote: > On 11/24/19 6:02 AM, Michael Rolnik wrote: > > Provide function disassembles executed instruction when `-d in_asm` is > > provided > > Maybe "Implement the disassemble_info::print_insn() callback wh

[PATCH v37 03/17] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/insn.decode | 194 + 1 file changed, 194 insertions(+) create mode 100644 target

[PATCH v37 01/17] target/avr: Add outward facing interfaces and core CPU logic

This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Co-developed-by: Michael Rolnik Co-developed-by: Sarah Harris Signed-off-by: Michael Rolnik Signed-off-by: Sarah Harris Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov Tested-by

[PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions

This includes: - ADD, ADC, ADIW - SBIW, SUB, SUBI, SBC, SBCI - AND, ANDI - OR, ORI, EOR - COM, NEG - INC, DEC - MUL, MULS, MULSU - FMUL, FMULS, FMULSU - DES Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 822

[PATCH v37 06/17] target/avr: Add instruction translation - Branch Instructions

This includes: - RJMP, IJMP, EIJMP, JMP - RCALL, ICALL, EICALL, CALL - RET, RETI - CPSE, CP, CPC, CPI - SBRC, SBRS, SBIC, SBIS - BRBC, BRBS Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 549

[PATCH v37 13/17] target/avr: Register AVR support with the rest of QEMU

Add AVR related definitions into QEMU Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- qapi/machine.json | 3 ++- include/disas/dis-asm.h| 6 ++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ tests

[PATCH v37 02/17] target/avr: Add instruction helpers

access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/helper.h | 29 target/avr/helper.c | 354 2 files changed, 383

[PATCH v37 07/17] target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 1123 1 file changed, 1123 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v37 00/17] QEMU AVR 8 bit cores

2. tename 1. NO_CPU_REGISTERS-> NUMBER_OF_CPU_REGISTERS 2. NO_IO_REGISTERS -> NUMBER_OF_IO_REGISTERS 3. to_A-> to_regs_16_31_by_one 4. to_B-> to_regs_16_23_by_one 5. to_C-> to_regs_24_30_by_two 6. to_D-> to_

[PATCH v37 15/17] target/avr: Add boot serial test

Print out 'T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth --- tests/boot-serial-test.c | 10 ++ tests/Makefile.include | 2 ++ 2 files changed, 12 insertions(+) diff --g

[PATCH v37 08/17] target/avr: Add instruction translation - MCU Control Instructions

This includes: - BREAK - NOP - SLEEP - WDR Signed-off-by: Michael Rolnik --- target/avr/translate.c | 174 + 1 file changed, 174 insertions(+) diff --git a/target/avr/translate.c b/target/avr/translate.c index dc6a1af2fc..54b384f00b

[PATCH v37 10/17] target/avr: Add instruction disassembly function

, r24 0x04c2: RET ... ``` Signed-off-by: Michael Rolnik Suggested-by: Richard Henderson Suggested-by: Philippe Mathieu-Daudé Suggested-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/cpu.h | 1 + target/avr/cpu.c

[PATCH v37 04/17] target/avr: Add instruction translation - Registers definition

Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 145 + 1 file changed, 145 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b

[PATCH v37 09/17] target/avr: Add instruction translation - CPU main translation function

Co-developed-by: Richard Henderson Co-developed-by: Michael Rolnik Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 234 + 1 file changed, 234 insertions(+) diff --git a/target/avr/translate.c b/target/avr

[PATCH v37 12/17] target/avr: Add example board configuration

A simple board setup that configures an AVR CPU to run a given firmware image. This is all that's useful to implement without peripheral emulation as AVR CPUs include a lot of on-board peripherals. NOTE: this is not a real board NOTE: it's used for CPU testing Signed-off-b

[PATCH v37 17/17] target/avr: Update MAINTAINERS file

Include AVR maintaners in MAINTAINERS file Signed-off-by: Michael Rolnik --- MAINTAINERS | 11 +++ 1 file changed, 11 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5e5e3e52d6..d7bfb62791 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,17 @@ S: Maintained F: hw

[PATCH v37 14/17] target/avr: Update build system

Make AVR support buildable Signed-off-by: Michael Rolnik Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic --- configure | 7 +++ default-configs/avr-softmmu.mak | 5 + target/avr/Makefile.objs| 34 + 3

[PATCH v37 16/17] target/avr: Add Avocado test

The test is based on https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out. it also demostrates that timer and IRQ are working Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé

[PATCH v37 11/17] target/avr: Add limited support for USART and 16 bit timer peripherals

include/hw/misc/avr_mask.h new file mode 100644 index 00..d3e21972d8 --- /dev/null +++ b/include/hw/misc/avr_mask.h @@ -0,0 +1,47 @@ +/* + * AVR Power Reduction + * + * Copyright (c) 2019 Michael Rolnik + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software

Re: [PATCH v36 11/17] target/avr: Add limited support for USART and 16 bit timer peripherals

+#define USART_CSRC_MSEL1 (1 << 7) > > > +#define USART_CSRC_MSEL0 (1 << 6) > > > +#define USART_CSRC_PM1(1 << 5) > > > +#define USART_CSRC_PM0(1 << 4) > > > +#define USART_CSRC_CSZ1 (1 << 2) > > > +#define USART_CSRC_CSZ0 (1 << 1) > > > > The previous definitions can go into hw/char/avr_usart.c. > > > > Why? > -- Best Regards, Michael Rolnik

Re: [RFC PATCH 00/10] hw/avr: Introduce the Arduino board

; hw/avr/Makefile.objs | 3 +- > tests/acceptance/machine_avr6.py | 10 +- > 11 files changed, 623 insertions(+), 291 deletions(-) > create mode 100644 hw/avr/atmega.h > create mode 100644 hw/avr/arduino.c > create mode 100644 hw/avr/atmega.c > delete mode 100644 hw/avr/sample.c > > -- > 2.21.0 > > -- Best Regards, Michael Rolnik

Re: [PATCH v37 01/17] target/avr: Add outward facing interfaces and core CPU logic

On Thu, Nov 28, 2019 at 12:26 AM Philippe Mathieu-Daudé wrote: > Hi Michael, > > On 11/27/19 6:52 PM, Michael Rolnik wrote: > > This includes: > > - CPU data structures > > - object model classes and functions > > - migration functions > > - GDB hooks

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

On Wed, Nov 27, 2019 at 11:06 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > On Wed, Nov 27, 2019 at 6:53 PM Michael Rolnik wrote: > > > > This series of patches adds 8bit AVR cores to QEMU. > > All instruction, except BREAK/DES/SPM/SPMX, are implemen

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

m> wrote: > > > On Thursday, November 28, 2019, Michael Rolnik wrote: > >> >> >> On Wed, Nov 27, 2019 at 11:06 PM Aleksandar Markovic < >> aleksandar.m.m...@gmail.com> wrote: >> >>> On Wed, Nov 27, 2019 at 6:53 PM Michael Rolnik >&

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

I will rename them. On Thu, Nov 28, 2019 at 3:41 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Thursday, November 28, 2019, Philippe Mathieu-Daudé > wrote: > >> On 11/28/19 2:25 PM, Michael Rolnik wrote: >> >>> I don't see

Re: [PATCH v37 12/17] target/avr: Add example board configuration

was where I stopped to care as I did (and still don't) want to model devices. I believed that others would join and add devices. then two years passed by, Sarah implemented the timer and the UART devices. And here we are. Regards, Michael Rolnik On Sat, Nov 30, 2019 at 12:49 PM Aleksandar Mar

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

-avr-cpu xmega2-avr-cpu xmega4-avr-cpu xmega5-avr-cpu xmega6-avr-cpu xmega7-avr-cpu Regards, Michael Rolnik On Sat, Nov 30, 2019 at 1:28 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Wednesday, November 27, 2019, Michael Rolnik wrote: > >> This ser

Re: [PATCH v35 01/13] target/avr: Add outward facing interfaces and core CPU logic

Aleksandar. if download AVR specs you can see that some cores implement some instructions and some don't. We could go other way, just implement all of them regardless of what is supported and what is not and hope that executed elf contains only supported ones. Regards, Michael Rolnik O

Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions

Hi Aleksandar. thanks for pointing that out I was not aware of that. I can fix it. Regards, Michael Rolnik On Sat, Nov 30, 2019 at 6:29 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Saturday, November 30, 2019, Aleksandar Markovic < > aleksandar.m.

Re: [PATCH v37 10/17] target/avr: Add instruction disassembly function

Aleksandar. If this code is going to be merge in 2019 I should modify al the copyrights, right. or should I put 2020 in? Regards, Michael Rolnik On Mon, Dec 2, 2019 at 2:28 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Wednesday, November 27, 2019, Michae

Re: [PATCH v37 05/17] target/avr: Add instruction translation - Arithmetic and Logic Instructions

Aleksandar. I could not find what happens if an instruction with unsupported registers is executed. So, I am leaving this tiny core for later. Regards, Michael Rolnik On Sun, Dec 1, 2019 at 1:11 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Saturday, No

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

.com> wrote: > >> >> >> On Saturday, November 30, 2019, Michael Rolnik wrote: >> >>> There is *-cpu *option where you can specify what CPU you want, if this >>> option is not specified avr6 (avr6-avr-cpu) is chosen. >>> >>> *./avr-sof

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

how can I get this elf flags from within QEMU? On Mon, Dec 2, 2019 at 4:01 PM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Monday, December 2, 2019, Michael Rolnik wrote: > >> No, I don't. >> but I also can load and execute a b

Re: [PATCH v37 00/17] QEMU AVR 8 bit cores

Aleksandar. enjoy your vacation. Regards, Michael Rolnik On Tue, Dec 3, 2019 at 3:48 AM Aleksandar Markovic < aleksandar.m.m...@gmail.com> wrote: > > > On Tuesday, December 3, 2019, Aleksandar Markovic < > aleksandar.m.m...@gmail.com> wrote: > >> >> >

Re: [PATCH v37 10/17] target/avr: Add instruction disassembly function

Hi Philippe. I copied Richard's file and modified it's content, that's why Richard is there. Regards, Michael Rolnik On Tue, Dec 3, 2019 at 1:18 PM Philippe Mathieu-Daudé wrote: > On 12/2/19 8:04 AM, Michael Rolnik wrote: > > Aleksandar. > > > > If this

[Qemu-devel] [PATCH for 4.2 v28 0/8] QEMU AVR 8 bit cores

late prr0/prr1 changes since v26 1. add avocado acceptence test 2. add boot serial test changes sicnce v27 1. list atmel2560 devices as unimplemented 2. fix sram base/size Michael Rolnik (4): target/avr: Add instruction decoding target/avr: Add instruction translation target/avr: Register

[Qemu-devel] [PATCH for 4.2 v28 3/8] target/avr: Add instruction decoding

This includes: - encoding of all 16 bit instructions - encoding of all 32 bit instructions Signed-off-by: Michael Rolnik --- target/avr/insn.decode | 175 + 1 file changed, 175 insertions(+) create mode 100644 target/avr/insn.decode diff --git a/target

[Qemu-devel] [PATCH for 4.2 v28 6/8] target/avr: Add example board configuration

PU testing Signed-off-by: Michael Rolnik --- hw/Kconfig | 1 + hw/avr/Kconfig | 5 + hw/avr/Makefile.objs | 1 + hw/avr/sample.c | 282 +++ 4 files changed, 289 insertions(+) create mode 100644 hw/avr/Kconfig create mode 100

[Qemu-devel] [PATCH for 4.2 v28 5/8] target/avr: Add limited support for USART and 16 bit timer peripherals

-off-by: Michael Rolnik --- hw/char/Kconfig| 3 + hw/char/Makefile.objs | 1 + hw/char/avr_usart.c| 322 ++ hw/misc/Kconfig| 3 + hw/misc/Makefile.objs | 2 + hw/misc/avr_mask.c | 110 ++ hw/timer

[Qemu-devel] [PATCH for 4.2 v28 2/8] target/avr: Add instruction helpers

wake interrupts. Memory access instructions are implemented here because some address ranges actually refer to CPU registers. Signed-off-by: Michael Rolnik --- target/avr/helper.c | 354 target/avr/helper.h | 29 2 files changed, 383 insertions

[Qemu-devel] [PATCH for 4.2 v28 8/8] target/avr: Add tests

#x27;T' through serial port Signed-off-by: Michael Rolnik Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- tests/Makefile.include | 2 ++ tests/acceptance/machine_avr6.py | 36 tests/boot-serial-test.c | 10 +

[Qemu-devel] [PATCH for 4.2 v28 7/8] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file

Signed-off-by: Michael Rolnik --- MAINTAINERS | 6 ++ arch_init.c | 2 ++ configure | 7 +++ default-configs/avr-softmmu.mak | 5 + include/disas/dis-asm.h | 6 ++ include/sysemu/arch_init.h | 1

[Qemu-devel] [PATCH for 4.2 v28 1/8] target/avr: Add outward facing interfaces and core CPU logic

From: Sarah Harris This includes: - CPU data structures - object model classes and functions - migration functions - GDB hooks Signed-off-by: Michael Rolnik Acked-by: Igor Mammedov --- gdb-xml/avr-cpu.xml| 49 target/avr/cpu-param.h | 37 +++ target/avr/cpu.c | 579

[Qemu-devel] [PATCH for 4.2 v28 4/8] target/avr: Add instruction translation

This includes: - TCG translations for each instruction Signed-off-by: Michael Rolnik --- target/avr/translate.c | 2888 1 file changed, 2888 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c b/target/avr

Re: [PATCH rc5 01/32] target/avr: Add basic parameters of the new platform

Tested-by: Michael Rolnik On Fri, Feb 7, 2020 at 3:58 AM Aleksandar Markovic < aleksandar.marko...@rt-rk.com> wrote: > From: Michael Rolnik > > This includes definitions of various basic parameters needed > for integration of a new platform into QEMU. > > [AM: Split a

Re: [PATCH rc4 06/29] target/avr: Add defintions of AVR core types

suggested by GCC gcc/config/avr/avr-devices.c <https://github.com/gcc-mirror/gcc/blob/master/gcc/config/avr/avr-devices.c> file and when a specific MCU is created it will set / reset CPU features relevant to it. I hope this helps. Best Regards, Michael Rolnik On Sat, Feb

Re: [PATCH qemu] hw: add ATmega16u4 and ATmega32u4 MCUs

Reviewed-by: Michael Rolnik On Sun, May 14, 2023 at 12:54 AM ~rmsyn wrote: > From: rmsyn > > Adds support for ATmega16u4 and ATmega32u4 MCU definitions. > > Defines interrupts, memory layout, and machine types for generic > ATmega16u4 and ATmega32u4 MCUs. > > Signed-of

Re: [PATCH v6 19/40] target/avr: Restrict has_work() handler to sysemu

Reviewed-by: Michael Rolnik On Fri, Sep 24, 2021 at 12:40 PM Philippe Mathieu-Daudé wrote: > Restrict has_work() to sysemu. > > Reviewed-by: Richard Henderson > Signed-off-by: Philippe Mathieu-Daudé > --- > target/avr/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [PATCH] target/avr: Optimize various functions using extract opcode

>> --- > >> target/avr/translate.c | 16 +--- > >> 1 file changed, 5 insertions(+), 11 deletions(-) > > > > Reviewed-by: Richard Henderson > > Do you mind taking this patch via tcg-next? > -- Best Regards, Michael Rolnik

Re: [PATCH 2/3] target/avr: Only execute one interrupt at a time

Reviewed-by: Michael Rolnik On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson < richard.hender...@linaro.org> wrote: > We cannot deliver two interrupts simultaneously; > the first interrupt handler must execute first. > > Signed-off-by: Richard Henderson > --- >

Re: [PATCH 1/3] target/avr: Call avr_cpu_do_interrupt directly

Reviewed-by: Michael Rolnik On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson < richard.hender...@linaro.org> wrote: > There is no need to go through cc->tcg_ops when > we know what value that must have. > > Signed-off-by: Richard Henderson > --- > target/avr/h

Re: [PATCH 3/3] target/avr: Disable interrupts when env->skip set

Reviewed-by: Michael Rolnik On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson < richard.hender...@linaro.org> wrote: > This bit is not saved across interrupts, so we must > delay delivering the interrupt until the skip has > been processed. > > Resolves: https://gitlab.

Re: [PATCH 0/3] target/avr: Fix skips vs interrupts

Reviewed-by: Michael Rolnik On Fri, Aug 26, 2022 at 11:55 PM Richard Henderson < richard.hender...@linaro.org> wrote: > Fixes https://gitlab.com/qemu-project/qemu/-/issues/1118 > > r~ > > Richard Henderson (3): > target/avr: Call avr_cpu_do_interrupt directly > t

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