et control registers.
Signed-off-by: Chalapathi V
Signed-off-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_nest_pervasive.c | 208
include/hw/ppc/pnv_nest_pervasive.h | 32 +
includ
and certain other proprietary firmware.
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/timebase_helper.c | 105 ---
target/ppc/translate.c | 42 +-
2 files changed, 136 insertions(+), 11 deletions(-)
diff --git a/target/ppc
-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 35 ++-
1 file changed, 10 insertions(+), 25 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f87d35379a..c140f3c96d 100644
--- a/target/ppc/mmu_helper.c
508238 7680722
After 34s 73 1143
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 43 +++--
1 file changed, 37 insertions(+), 6
From: Philippe Mathieu-Daudé
Check tcg_enabled() before calling softmmu_resize_hpt_prepare()
and softmmu_resize_hpt_commit() to allow the compiler to elide
their calls. The stubs are then unnecessary, remove them.
Reviewed-by: Nicholas Piggin
Signed-off-by: Philippe Mathieu-Daudé
Signed-off
cc99318 ("docs/devel: rationalise unstable gitlab tests under
FLAKY_TESTS") changed this to being flaky but it isn't really, it just
had a long runtime.
So take the SPEED=slow variable from qtests and introduce it to avocado,
and make these tests require it.
Reviewed-by: Cédric Le Goater
From: Saif Abrar
SPR's CFAR, DEC, HDEC, TB-L/U are not implemented as part of CPUPPCState.
Hence, gdbstub is not able to access them using (CPUPPCState *)env->spr[] array.
Update gdb_get_spr_reg() method to handle these SPR's specifically.
Signed-off-by: Saif Abrar
Signed-off-by: Nicho
POWER CPUs support hash and radix MMU modes. Linux supports running in
either mode, but defaults to radix. To keep up testing of QEMU's hash
MMU implementation, add some Linux hash boot tests.
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_powernv.py | 23 +++
tests
- Connected GPIO pin tests of P10 PCA9552 device. Tests
output of pins 0-4 affect input of pins 5-9 respectively.
- PCA9554 GPIO pins test. Tests input and ouput functionality.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_i2c.c
Signed-off-by: Nicholas Piggin
---
hw/misc/pca9552.c | 50 +--
include/hw/misc/pca9552.h | 3 ++-
2 files changed, 45 insertions(+), 8 deletions(-)
diff --git a/hw/misc/pca9552.c b/hw/misc/pca9552.c
index f00a149d61..2ae13af35e 100644
--- a/hw/misc
,
still in use by old distros.
Reviewed-by: Thomas Huth
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
docs/about/deprecated.rst | 8
hw/ppc/spapr.c| 1 +
roms/skiboot | 2 +-
3 files changed, 10 insertions
lenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 78f5c6262a..97bdfb2d1e 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1900,7 +1900,19 @@ static void pnv_rainie
and
copyrights from the original spapr_hcall.c at commit 9fdf0c2995.
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Update file description.]
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_softmmu.c | 9 +
1 file changed, 9 insertions(+)
but is instead named similarly to boot_linux.
Reviewed-by: Warner Losh
Signed-off-by: Nicholas Piggin
Unfortunately the latest stable (14.0) x86-64 VM image does not seem to
output to console by default and I've not been able to find a reliable
way to edit the filesystem to change the boot loader
image, boots it and downloads and installs
the qemu package, then boots a virtual machine under it, re-using the
original Alpine VM image.
Signed-off-by: Nicholas Piggin
---
MAINTAINERS | 1 +
tests/avocado/ppc_hv_tests.py | 203 ++
2 files
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2108
Fixes: 55a7fa34f89 ("target/ppc: Machine check on invalid real address access
on POWER9/10")
Fixes: 5a5d3b23cb2 ("target/ppc: Add SRR1 prefix indication to interrupt
handlers")
Signed-off-by: Nicholas Piggin
---
targ
Use the default CPU with the pseries machine unless there is a
specific requirement.
Signed-off-by: Nicholas Piggin
---
tests/avocado/migration.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 09b62f813e..be6234b3c2 100644
Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index 3f0180e1f8..af104fff1c 100644
--- a/tests/avocado
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 31 +++
1 file changed, 23 insertions
Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
MAINTAINERS| 10 +-
hw/misc/pca9554.c | 328 +
include/hw/misc/pca9554.h | 36
include/hw/misc/pca9554_regs.h | 19 ++
4 files changed, 391 insertions
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 15
hw/ppc/pnv_chiptod.c | 132 +++
include/hw/ppc/pnv.h | 2 +
include/hw/ppc/pnv_chiptod.h | 4 ++
target/ppc/cpu.h | 13
5 files changed, 166 insertions
scenario. Existing code was doing the opposite
and setting INPUT0/1 bit to a 1 when the LSn bit was
set to 0, so this commit fixes that.
Reviewed-by: Andrew Jeffery
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/misc/pca9552.c | 18 +-
tests/qtest
, because the QEMU ppc timebase
implementation is always synchronised acros all cores.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_chiptod.c | 454 +++
hw/ppc/trace-events | 4
-by: Nicholas Piggin
---
target/ppc/cpu.h | 36 ++
target/ppc/timebase_helper.c | 210 ++-
2 files changed, 243 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 0e932838aa..ec14574d14 100644
--- a/target/ppc/cpu.h
users should be low.
QEMU should follow the ISA for register name convention (where there is
no established GDB name).
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c| 20 ++--
target/ppc/helper_regs.c | 2 +-
2 files changed, 11 insertions
/spapr: Introduce SPAPR_IRQ_NR_IPIS to refer IRQ range for CPU IPIs.
ppc/spapr: Initialize max_cpus limit to SPAPR_IRQ_NR_IPIS.
Nicholas Piggin (28):
target/ppc: Fix lxv/stxv MSR facility check
target/ppc: Fix crash on machine check caused by ifetch
tests/avocado: mark
Add test for POWER10.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index af104fff1c..a00202df3c 100644
ppc has no avocado tests for the KVM backend. Add a KVM boot_linux.py
test for pseries.
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index de4c8805f7
Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.
Tested-by: BALATON Zoltan
Acked-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 2 +-
1
interface so that
all child buses and devices are automatically reset.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_i2c.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc
POWER10 is the latest pseries CPU.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0028ce0b67..b442d18317 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 8
target/ppc/helper_regs.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
From: Chalapathi V
This part of the patchset connects the nest1 chiplet model to p10 chip.
Signed-off-by: Chalapathi V
Signed-off-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 15 +++
include/hw/ppc/pnv_chip.h | 2 ++
2 files changed, 17
On Tue Dec 12, 2023 at 7:19 AM AEST, Philippe Mathieu-Daudé wrote:
> 'abi_ptr' is a user specific type. The system emulation
> equivalent is 'target_ulong'. Use it in ppc_ldl_code()
> to emphasis this is not an user emulation function.
>
> Signed-off-by: Philippe Mathieu-Daudé
Ack
On Tue Dec 12, 2023 at 7:19 AM AEST, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Nicholas Piggin
> ---
> hw/ppc/spapr_hcall.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index 5
ot;cpu-param.h". The last one
> in "cpu.h", with a bunch of definitions irrelevant for
> TCG. By moving the TCG_GUEST_DEFAULT_MO definition to
> "cpu-param.h", we can simplify various accel/tcg includes.
Acked-by: Nicholas Piggin (ppc)
Thanks,
Nick
cc99318 ("docs/devel: rationalise unstable gitlab tests under
FLAKY_TESTS") changed this to being flaky but it isn't really, it just
had a long runtime.
So take the SPEED=slow variable from qtests and introduce it to avocado,
and make these tests require it.
Reviewed-by: Cédric Le Goater
image, boots it and downloads and installs
the qemu package, then boots a virtual machine under it, re-using the
original Alpine VM image.
Signed-off-by: Nicholas Piggin
---
MAINTAINERS | 1 +
tests/avocado/ppc_hv_tests.py | 203 ++
2 files
ppc has no avocado tests for the KVM backend. Add a KVM boot_linux.py
test for pseries.
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux.py b/tests/avocado/boot_linux.py
index 7c9cf6ae15
Have 440 tlbwe flush only the range corresponding to the addresses
covered by the software TLB entry being modified rather than the
entire TLB. This matches what 4xx does.
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
space) changes.
- If low prot (access control) bits change.
Fix this by removing tricks to avoid TLB flushes, and just invalidate
the TLB if any valid entry is being changed, similarly to 4xx.
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 35 ++-
1
this uses guestfish to extract the kernel and initrd
and boot them directly.
Signed-off-by: Nicholas Piggin
---
tests/avocado/replay_linux.py | 76 ++-
1 file changed, 75 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/replay_linux.py b/tests/avocado
Flushing the TCG TLB pages that cache a software TLB is a common
operation, factor it into its own function.
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target
this does not get a ppc_ prefix
but is instead named similarly to boot_linux.
Reviewed-by: Warner Losh
Signed-off-by: Nicholas Piggin
Unfortunately the latest stable (14.0) x86-64 VM image does not seem to
output to console by default and I've not been able to find a reliable
way to edit the filesystem
does not have a boot loader and not sure how to pass boot options to
FreeBSD kernel directly.
Haven't done the BE FreeBSD test yet that Cedric suggested, will save
that for later.
Thanks,
Nick
Nicholas Piggin (8):
tests/avocado: mark boot_linux.py long runtime instead of flaky
tests/avocado
POWER CPUs support hash and radix MMU modes. Linux supports running in
either mode, but defaults to radix. To keep up testing of QEMU's hash
MMU implementation, add some Linux hash boot tests.
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_powernv.py | 23 +++
tests
4 s)
boot_linux.py:BootLinuxX8664.test_pc_q35_tcg: PASS (97.05 s)
boot_linux.py:BootLinuxPPC64.test_pseries_tcg: PASS (148.86 s)
boot_linux.py:BootLinuxS390X.test_s390_ccw_virtio_tcg: PASS (149.83 s)
So mark the x86-64 tests as SPEED=slow as well.
Signed-off-by: Nicholas Piggin
The other way
that cover the same address and address space, but that
is a programming error and results in undefined behaviour, and flushing
does not give an obviously better outcome in that case either.
Remove the unnecessary flush of a newly written software TLB entry.
Signed-off-by: Nicholas Piggin
508238 7680722
After 34s 73 1143
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 43 +++--
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/target/ppc/mmu_helper.c b/target
Rather than tlbwe_lo always flushing all TCG TLBs, have it flush just
those corresponding to the old software TLB, and only if it was valid.
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_helper.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/ppc
Add test for POWER10.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
tests/avocado/boot_linux_console.py | 8
1 file changed, 8 insertions(+)
diff --git a/tests/avocado/boot_linux_console.py
b/tests/avocado/boot_linux_console.py
index 3f0180e1f8..4f05bb7441 100644
On Thu Jan 18, 2024 at 8:34 AM AEST, dan tan wrote:
> The handling of the following two registers are added -
> DAWR1 (0x0bd, 189) - Data Address Watchpoint 1
> DAWRX1 (0x0b5, 181) - Data Address Watchpoint Extension 1
>
> Signed-off-by: dan tan
Small nit,
On Thu Jan 18, 2024 at 8:34 AM AEST, dan tan wrote:
> The handling of the following SPRs are added -
> ITV1 (0x375, 885) - noop (not in Power10 ISA)
I can't see where this is defined. Not in P10 user manual AFAIKS?
> SIER2 (0x2f0, 752) - Sampled Instruction Event Register 2
of the PAPR hypervisor
interface (called vhyp).
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Pick a different name, explain it in changelog.]
Signed-off-by: Nicholas Piggin
---
hw/ppc/{spapr_softmmu.c => spapr_vhyp_mmu.c} | 0
hw/ppc/meson.build | 2 +-
2 fi
and
copyrights from the original spapr_hcall.c at commit 9fdf0c2995.
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Update file description.]
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_softmmu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/hw/ppc/spapr_softmmu.c b/hw/ppc/s
From: Philippe Mathieu-Daudé
Since 'softmmu' is quite a loaded term in QEMU, rename the vhyp MMU
facilities to use the vhyp_mmu_ prefix rather than softmmu_.
Signed-off-by: Philippe Mathieu-Daudé
[npiggin: Pick a different name.]
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/spapr.h | 9
From: Philippe Mathieu-Daudé
Check tcg_enabled() before calling softmmu_resize_hpt_prepare()
and softmmu_resize_hpt_commit() to allow the compiler to elide
their calls. The stubs are then unnecessary, remove them.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
---
hw
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv.h | 2 +
include/hw/ppc/pnv_chiptod.h | 4 ++
target/ppc/cpu.h | 13
hw/ppc/pnv.c | 15
hw/ppc/pnv_chiptod.c | 132 +++
5 files changed, 166 insertions
The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 5aa1ed474a..452b266e8b 100644
--- a/hw/ppc
/2108
Fixes: 55a7fa34f89 ("target/ppc: Machine check on invalid real address access
on POWER9/10")
Fixes: 5a5d3b23cb2 ("target/ppc: Add SRR1 prefix indication to interrupt
handlers")
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 32 +---
, because the QEMU ppc timebase
implementation is always synchronised acros all cores.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
include/hw/ppc/pnv_chiptod.h | 49
include/hw/ppc/pnv_xscom.h | 9 +
hw/ppc/pnv_chiptod.c | 454
and mfbhrbe instructions
target/ppc: Add migration support for BHRB
Nicholas Piggin (21):
target/ppc: Fix crash on machine check caused by ifetch
target/ppc: Prevent supervisor from modifying MSR[ME]
spapr: set MSR[ME] and MSR[FP] on client entry
target/ppc: Rename registers to match ISA
Prevent guest state modifying the MSR[ME] bit. Per ISA:
An attempt to modify MSRME in privileged but non-hypervisor state is
ignored (i.e., the bit is not changed).
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target
users should be low.
QEMU should follow the ISA for register name convention (where there is
no established GDB name).
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c| 20 ++--
target/ppc/helper_regs.c | 2 +-
2 files changed, 11 insertions(+), 11 deletions(-)
diff
ted).
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 8287494c39..b732a1b06e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -920,6 +920,18 @@ static v
The DECAR SPR is 32-bits width.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 421900cd11..8287494c39 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 6 +-
target/pp
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Signed-off-by: Nicholas Piggin
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 26 ++
2 files changed, 28 insertions(+)
diff --git
-by: Nicholas Piggin
---
target/ppc/cpu.h | 36 ++
target/ppc/timebase_helper.c | 210 ++-
2 files changed, 243 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9d115e539e..54150d5a08 100644
--- a/target/ppc/cpu.h
as normal with the exception that the mfbhrbe instruction will
always return a zero value.
Signed-off-by: Glenn Miles
[npiggin: rebase and minor compile fixes]
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 7
target/ppc
, which should be good
enough for QEMU debugging.
Signed-off-by: Nicholas Piggin
---
Since v1:
- New patch that also uses checkstop function
Since v2:
- Include support for 970.
- Add class attn enable check, similar to check_pow.
---
target/ppc/cpu.h | 16 +++-
target/ppc/helper.h
error. CPU registers are dumped.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Fix loop exit so it stops on the checkstop-causing instruction, rather than
after it.
Since v2:
- Use qemu_system_guest_panicked rather than vm_stop (Richard)
- Move away from printing to stderr (Zoltan)
- Reduce
Try these again. checkstop fix is mostly unchanged since last
posted, but several fixes to attn. Seems to work well enough.
Thanks,
Nick
Nicholas Piggin (2):
target/ppc: Make checkstop actually stop the system
target/ppc: Implement attn instruction on BookS 64-bit processors
target/ppc
POWER10 is the latest pseries CPU.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e8dabc8614..021b1a00e1 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4675,7 +4675,7 @@ static
Oops, these two should be with the previous series too.
Thanks,
Nick
Nicholas Piggin (2):
ppc/spapr: change pseries machine default to POWER10 CPU
ppc/pnv: Change powernv default to powernv10
hw/ppc/pnv.c | 4 ++--
hw/ppc/spapr.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions
POWER10 is the latest IBM Power machine. Although it is not offered in
"OPAL mode" (i.e., powernv configuration), so there is a case that it
should remain at powernv9, most of the development work is going into
powernv10 at the moment.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c |
state
MMCR0[FCPC] - A modifier for MMCR0[FCP]
MMCRA[BHRBRD] - Disables all BHRB recording for a thread
Signed-off-by: Glenn Miles
[npiggin: rebase and minor compile fixes]
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 5 +
target/ppc/helper.h
and certain other proprietary firmware.
Signed-off-by: Nicholas Piggin
---
target/ppc/timebase_helper.c | 105 ---
target/ppc/translate.c | 42 +-
2 files changed, 136 insertions(+), 11 deletions(-)
diff --git a/target/ppc/timebase_helper.c b/target
From: Glenn Miles
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Signed-off-by: Glenn Miles
---
target/ppc/machine.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index
TCG does not support copy/paste instructions. Remove it from
ibm,pa-features when running TCG. Similarly to SAO, there is a
migration issue here, but this doesn't really make things worse,
a cap would be required to fix it.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 12
1
This includes a number of improvements and fixes. Importantly there
is a change for QEMU platforms to permit the ChipTOD to be initialised
if it is present in the device tree. This will facilitate ChipTOD
enablement in pnv.
Signed-off-by: Nicholas Piggin
---
[blob omitted, patch is just
POWER10 hardware implements a degenerate transactional memory facility
in POWER8/9 PCR compatibility modes to permit migration from older
CPUs, but POWER10 / ISA v3.1 mode does not support it so the CPU model
should not support it.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 4
This allows different pa-features for powernv8/9/10.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4969fbdb05..0a144402d7 100644
--- a/hw/ppc/pnv.c
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 1e1946de59..2f58d8f292 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -265,6 +265,36 @@ static void
These are some patches to move defaults to Power10 CPU, update
some feature bits, and also update skiboot to 7.1. I would like
to do this for 9.0 if possible.
Thanks,
Nick
Nicholas Piggin (8):
target/ppc: POWER10 does not have transactional memory
ppc/spapr|pnv: Remove SAO from pa-features
SAO is a page table attribute that strengthens the memory ordering of
accesses. QEMU with MTTCG does not implement this, so clear it in
ibm,pa-features. There is a complication with spapr migration that is
addressed with comments, it is not a new problem here.
Signed-off-by: Nicholas Piggin
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 10 +-
1 file changed, 5 insert
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 68 --
hw/ppc/spapr.c | 1 +
2 files changed, 67 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv.c b
This matches the NMI injection helper function.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_events.c| 3 +--
target/ppc/excp_helper.c | 7 +++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index cb0587..4be9a5ba3a
Like commit 9cb805fd26 ("cpus: Define callback for QEMU "nmi" command")
this implements a machine check injection command framework and defines
a monitor command for ppc.
Signed-off-by: Nicholas Piggin
---
include/hw/nmi.h | 20
include/monit
]
MCE: CPU0: PID: 495 Comm: a NIP: [000130ee07c8]
MCE: CPU0: Initiator CPU
MCE: CPU0: Unknown
[ 71.567193] MCE: CPU0: NIP: [c00d7f6c] plpar_hcall_norets+0x1c/0x28
[ 71.567249] MCE: CPU0: Initiator CPU
[ 71.567308] MCE: CPU0: Unknown
Signed-off-by: Nicholas Piggin
equivalent,
and since better error injection might take some time, I'd like to
just hold nose and take this for now.
Thanks,
Nick
Nicholas Piggin (4):
nmi: add MCE class for implementing machine check injection commands
ppc/spapr: Implement mce injection
target/ppc: Add machine check interrupt
This implements mce injection for pnv.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
hw/ppc/pnv.c | 55
2 files changed, 56 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index aa22523316..b046a12f8c 100644
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/helper_regs.c | 31 +++
1 file changed, 23 insertions
PPR32 provides access to the upper half of PPR.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 1 +
target/ppc/spr_common.h | 2 ++
target/ppc/cpu_init.c | 12
target/ppc/translate.c | 16
4 files changed, 31 insertions(+)
diff --git a/target
Signed-off-by: Glenn Miles
[npiggin: rebase and minor compile fixes]
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 17 +
target/ppc/power8-pmu.h| 7 ++
target/ppc/cpu_init.c | 37 +-
target/ppc/power8-pmu.c
I grabbed Philippe's series series and tried to use a more
agreeable name. Further disagreement is okay, but must come
with a better alternative :) would be good to get this out of
the way. I actually don't think softmmu is a great term for it
either even in isolation, so would be good to move
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++
2 files changed, 12 insertions(+)
diff --git a/target/ppc/cpu.h b/target
to TBL, TBU, WR_TBL, WR_TBU, respectively.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 8
target/ppc/helper_regs.c | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index
701 - 800 of 1716 matches
Mail list logo
