Urgent---- *Circuit Design/Verification Engineer (QPI/PCIe, StarRC-XT, Pathmill, Prime-time, RTL, DRC, LVS)* at OR
Please send the resumes only on *s...@cy-tec.com* *Verification/Circuit Design Engineer* Location Hillsboro, OR Long Term Contract *Rate is $50/hr max* Description: Project involving *Electromagnetic QPI/PCIe probing …* (MUST HAVE) Requirements: The successful candidate will have demonstrable knowledge of transistor level circuit design and optimization at a level that meets with basic requirements for the position - Use and familiarity with timing tools (*Pathmill, Prime-time*), *Parasitic extraction (StarRC-XT), transistor circuit simulation, mixed signal validation (VCS(R) and/or nanosim(R), ADMS), Register Transfer Level (RTL)* to schematic verification tools *(Verplex and/or Conformal), and Design Rule Checking (DRC) and/or LVS (Hercules) * - Ability to work well in a diverse team environment - Excellent written and verbal communications skills - A minimum of three years of previous experience and/or exposure to the design of *IOs, PLLs, DLLs* or memories design experience Additional Skills Desired (Nice to Have): Design experience with high speed serial *IO, QPI or PCIe** would be an added advantage Daily Responsibilities include: Run and analyze analog and/or digital circuit simulations. Make the necessary modifications for circuits to meet performance targets. - Run layout extraction. - Work with the mask design team to ensure layout is completed to engineering requirements. - Run static timing analysis for digital circuits and ensure they meet performance targets. - Perform Function Equivalence Verification - Validate circuit functionality with mixed signal verification. Thanks and Regards Syed Muzaffer Ali CyberTec Inc 703 544 3910 Please send the resumes only on *s...@cy-tec.com* *Verification/Circuit Design Engineer* Location Hillsboro, OR Long Term Contract *Rate is $50/hr max* Description: Project involving *Electromagnetic QPI/PCIe probing …* (MUST HAVE) Requirements: The successful candidate will have demonstrable knowledge of transistor level circuit design and optimization at a level that meets with basic requirements for the position - Use and familiarity with timing tools (*Pathmill, Prime-time*), *Parasitic extraction (StarRC-XT), transistor circuit simulation, mixed signal validation (VCS(R) and/or nanosim(R), ADMS), Register Transfer Level (RTL)* to schematic verification tools *(Verplex and/or Conformal), and Design Rule Checking (DRC) and/or LVS (Hercules) * - Ability to work well in a diverse team environment - Excellent written and verbal communications skills - A minimum of three years of previous experience and/or exposure to the design of *IOs, PLLs, DLLs* or memories design experience Additional Skills Desired (Nice to Have): Design experience with high speed serial *IO, QPI or PCIe** would be an added advantage Daily Responsibilities include: Run and analyze analog and/or digital circuit simulations. Make the necessary modifications for circuits to meet performance targets. - Run layout extraction. - Work with the mask design team to ensure layout is completed to engineering requirements. - Run static timing analysis for digital circuits and ensure they meet performance targets. - Perform Function Equivalence Verification - Validate circuit functionality with mixed signal verification. Thanks and Regards Syed Muzaffer Ali CyberTec Inc 703 544 3910 --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "REQSRESUMES" group. To post to this group, send email to reqsresumes@googlegroups.com To unsubscribe from this group, send email to reqsresumes+unsubscr...@googlegroups.com For more options, visit this group at http://groups.google.com/group/reqsresumes?hl=en -~----------~----~----~----~------~----~------~--~---
