You
HOPE YOU ARE DOING WELL!
PLEASE FIND BELOW JOB DESCRIPTION FOR YOUR REVIEW. PLEASE SEND ME YOUR
UPDATED COPY OF RESUME AT a...@intellyk.com OR REACH ME AT (916)
655-2007
JOB TITLE: DESIGN VERIFICATION ENGINEER
LOCATION: SANTA CLARA, CA
EMPLOYMENT TYPE: FULL TIME / CONTRACT
JOB DESCRIPTION:
ROLE & RESPONSIBILITIES
* Develop full chip level test plan, Verilog based full chip test
bench components.
* Familiar with writing, running and debugging C/C++ based tests.
* Close Functional/Code coverage.
* Ability to independently execute on test plan, run simulations and
debug.
DESIRABLE:
* Previous experience with PCIe, HBM-DDR, Ethernet, SPI, I2C, JTAG,
Debug highly desired.
* Gate simulation, Power Aware simulation highly desired.
* Scripting skills (Perl, Python).
* Emulation experience a plus.
REGARDS,
ARUN BHATIA
TECHNICAL RECRUITER
[cid:image001.jpg@01D535B0.A49E1F40]
15 CORPORATE PL S, SUITE #450
PISCATAWAY TOWNSHIP, NJ 08854
DESK: (732) 624-6445 / EXTN:308
DIRECT: 916-655-2007
EMAIL: a...@intellyk.com
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