Wow nice one, I wonder how these reflect to the original zilog timings
C
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Edwin Blink
Sent: 01 February 2004 20:06
To: sam-users@nvg.ntnu.no
Subject: Z80 Timings
Hi all
I decided to make a simple hardware
Edwin Blink wrote:
IN A,(n) 12 Ts (all ports)
The original tests I did for SimCoupé showed ports F8 to FF always
required ASIC attention, giving an extra 4 tstate penalty if not correctly
aligned (even in the border area). Just in case your test avoided it, could
you try it with a NOP
From: Chris White [EMAIL PROTECTED]
Wow nice one, I wonder how these reflect to the original zilog timings
Will include the original times in the list I will create too.
Previously I rounded common instructions to multiples of 4 and it worked for
me.
But now i'm puzzled ... I just found out
But now i'm puzzled ... I just found out that a LDI takes 19 Ts instead
of
20 !
Sorry It is 20 (Phew!) no 19 Like i mentioned before. I use the E
register to save the old counter value in and I forgot that it gets
increased
by LDI(r) instructions.
Well I better call it a day
Edwin
From: Simon Owen [EMAIL PROTECTED]
The original tests I did for SimCoupé showed ports F8 to FF always
required ASIC attention, giving an extra 4 tstate penalty if not correctly
aligned (even in the border area).
Yeah your Right! But there are still some oddities. In one case I tested
when the
