On Thu, 2013-02-14 at 20:48 +, David Woodhouse wrote:
On Thu, 2013-02-14 at 18:10 +, Ian Campbell wrote:
I tested:
HEAD is now at e62d172 Make Xen one of the top-level build target choices
with the attached config and I'm afraid it booted from the cdrom no
matter what I did in
On Fri, 2013-02-15 at 11:19 +0400, Michael Tokarev wrote:
This patch is more than 2 years old and is applied to all more or
less recent qemu versions.
RHEL 6.3?
I'm *not* seeing this bug with recent qemu versions.
This does not tell us why disabling kvm (with this patch applied!)
makes a
On Thu, 2013-02-14 at 16:46 +, Ian Campbell wrote:
Right, we really need to find someone with hours to finish properly
integrating OVMF.
Hm, that 'someone' may end up being me¹.
So... from the Xen point of view, what needs doing? There are some
things on my TODO list which apply to
(removing edk2-devel, adding Jan)
On 02/15/13 08:19, Michael Tokarev wrote:
15.02.2013 07:43, Kevin O'Connor wrote:
On Fri, Feb 15, 2013 at 04:10:59AM +0100, Laszlo Ersek wrote:
On 02/15/13 02:22, Kevin O'Connor wrote:
On Thu, Feb 14, 2013 at 08:16:02PM -0500, Kevin O'Connor wrote:
By
On 02/14/13 23:24, David Woodhouse wrote:
On Thu, 2013-02-14 at 21:41 +0100, Laszlo Ersek wrote:
I noticed that under OVMF + SeaBIOS CSM + your related patches for both,
reset requested by the guest doesn't work as expected. The behavior is
an infinite loop, with the following debug fragment
This enables interrupts to work pre-boot for assigned devices.
I had self nak'd and resent a v2 patch for 2/2, but there were never
any comments, so resending the whole series as v2. Thanks,
Alex
---
Alex Williamson (2):
seabios q35: Enable all PIRQn IRQs at startup
seabios q35:
We seem to use the IRQEN bit of the PIRQn registers interchangeably
to select APIC mode or to disable an IRQ. I can't decide if we're
intending to disable the IRQ or select APIC mode here, but in either
case it prevents PIC mode assigned devices from working. When seabios
writes IRQEN to these
q35/ich9 doesn't use the same interrupt mapping function as
i440fx/piix. PIRQA:D and PIRQE:H are programmed identically, but we
start at index 0, not index -1. Slots 25 through 31 are also
programmed independently.
When running qemu w/o this patch, a device at address 0:6.0 will have
its PCI
On Fri, 2013-02-15 at 19:54 +0100, Laszlo Ersek wrote:
Same infinite loop, alas...
(i) What is your host kernel exactly?
3.7.5-201.fc18.x86_64 (booted from EFI on a MacBookPro 8,3).
(ii) And when you say you did a legacy boot, does that mean you installed
the guest OS as a traditional one?
On Thu, Feb 14, 2013 at 10:34:32AM +0100, Christian Gmeiner wrote:
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
Thanks. I committed this series.
-Kevin
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On Thu, Feb 14, 2013 at 10:54:57AM +0530, Avik Sil wrote:
cntl-regs should not be accessed before initializing it.
Thanks. I committed your patch.
-Kevin
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On 2/11/2013 at 10:11 AM, in message
20130211021114.GA14726@morn.localdomain,
Kevin O'Connor ke...@koconnor.net wrote:
On Wed, Feb 06, 2013 at 11:23:26PM -0500, Kevin O'Connor wrote:
On Mon, Feb 04, 2013 at 02:06:23PM +0800, Bo Yang wrote:
Latest iasl generate .lst as 'number: '
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