Re: [SeaBIOS] [Qemu-devel] [RFC PATCH v3 3/3] fw/pci: Allocate IGD stolen memory

2016-02-16 Thread Gerd Hoffmann
Hi, > I don't mind the allocation of guest memory issue, the fact that guest > memory is consumed by built-in devices is exactly what happens on bare > metal. And following in qemu what happens on bare metal usually works best long-term. > to pre-populate it, we could. It at least puts QEMU i

[SeaBIOS] [PATCH] ld: fix .text section address alignment

2016-02-16 Thread Roger Pau Monne
According to the output from readelf, the .text section should be aligned to 16: Section Headers: [Nr] Name TypeAddr OffSize ES Flg Lk Inf Al [ 0] (null)NULL 00 00 00 0 0 0 [ 1] .text PROGBITS

Re: [SeaBIOS] [SEABIOS] Plans for either 1.9.1 or 1.10.0?

2016-02-16 Thread Ian Campbell
On Mon, 2016-02-15 at 09:40 +0100, Gerd Hoffmann wrote: >   Hi, > > > 1.9-stable created now, with the patch above cherry-picked. > > 1.9.1 tagged & tarball uploaded now. Thanks for the heads up! ___ SeaBIOS mailing list SeaBIOS@seabios.org http://www

Re: [SeaBIOS] [PATCH] ld: fix .text section address alignment

2016-02-16 Thread Kevin O'Connor
On Tue, Feb 16, 2016 at 01:56:26PM +0100, Roger Pau Monne wrote: > According to the output from readelf, the .text section should be aligned to > 16: > > Section Headers: > [Nr] Name TypeAddr OffSize ES Flg Lk Inf > Al > [ 0] (null)NULL

Re: [SeaBIOS] [PATCH] ld: fix .text section address alignment

2016-02-16 Thread Roger Pau Monné
El 16/2/16 a les 17:33, Kevin O'Connor ha escrit: > On Tue, Feb 16, 2016 at 01:56:26PM +0100, Roger Pau Monne wrote: >> According to the output from readelf, the .text section should be aligned to >> 16: >> >> Section Headers: >> [Nr] Name TypeAddr OffSize ES Fl

[SeaBIOS] [RFC PATCH v4] fw/pci: Add support for mapping Intel IGD via QEMU

2016-02-16 Thread Alex Williamson
QEMU provides two fw_cfg files to support IGD. The first holds the OpRegion data which holds the Video BIOS Table (VBT). This needs to be copied into reserved memory and the address stored in the ASL Storage register of the device at 0xFC offset in PCI config space. The OpRegion is generally 8KB.

[SeaBIOS] INT 1A - PCI Services supported?

2016-02-16 Thread Bob Moore
Hello again, I have a need in my option ROM to interrogate devices identified by the BIOS PCI bus enumeration process. It seems like the most straight forward way to do this would be to use INT 1A assuming seaBios supports PCI 2.0 or later, to search for all instances of devices which I'm inte